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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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DP83256 Arkusz danych(PDF) 7 Page - Texas Instruments |
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DP83256 Arkusz danych(HTML) 7 Page - Texas Instruments |
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7 / 146 page  20 Architecture Description (Continued) Transmitter The Transmitter Block accepts 10-bit bytes composed of 8 bits data 1 bit parity and 1 bit control information from the Configuration Switch The Transmitter Block performs the following operations Encodes the data from 4B to 5B coding Filters out code violations from the data stream Generates Idle Master Halt Quiet or other user defined symbol pairs upon request Converts the data stream from NRZ to NRZI format for transmission Provides smoothing function when necessary During normal operation the Transmitter Block presents se- rial data to the PMD transmitter While in Internal Loopback mode the Transmitter Block presents serial data to the Re- ceiver Block While in the External Loopback mode the Transmitter Block presents serial data to the Clock Recov- ery Module Clock Generation Module The Clock Generation Module is an integrated phase locked loop that generates all of the required clock signals for the PLAYERa device and an FDDI system from a single 125 MHz reference The Clock Generation Module features High precision clock timing generated from a single 125 MHz reference Multiple precision phased (8 ns16 ns) 125 MHz Local Byte Clocks to eliminate timing skew in large multi-board concentrator configurations LBC timing which is insensitive to loading variations over a wide range (20 pF to 70 pF) of LBC loads A selectable dual frequency system clock Low clock edge jitter due to high VCO stability Station Management (SMT) Support The Station Management Support Block provides a number of useful features to simplify the implementation of the Con- nection Management (CMT) portion of SMT These features eliminate the time critical CMT response time constraints imposed by PC React and CF React times Integrated counters and timers eliminate the need for addi- tional external devices The following are the CMT features supported PC React CF React Auto Scrubbing (TCF Timer) Timer Idle Detection (TID Timer) Noise Event Counter (TNE Timer) Link Error Monitor (LEM Counter) 22 INTERFACES The PLAYERa device connects to other devices via five functional interfaces PMD Interface PHY Port Interface Control Bus Interface Clock Interface and the Miscellane- ous Interface PMD Interface The PMD Interface connects the PLAYERa device to a standard FDDI Physical Media Connection such as a fiber optic transceiver or a copper twisted pair transceiver It is a 125 MHz full duplex serial connection The DP83256-AP and DP83257 PLAYERa devices contain two PMD interfaces The Primary PMD Interface should be used for all PMD implementations that do not require an external scramblerdescrambler function clock recovery function or clock generation function such as a Fiber Optic or Shielded Twisted Pair (SDDI) PMD The second Alter- nate PMD Interface can be used to support Unshielded Twisted Pair (UTP) PMDs that require external scrambling and allows implementation with no external clock recovery or clock generation functions required PHY Port Interface The PHY Port Interface connects the PLAYERa device to one or more MAC devices andor PLAYERa devices Each PHY Port Interface consists of two byte-wide interfaces one for PHY Request data input to the PLAYERa device and one for the PHY Indicate data output of the PLAYERa de- vice Each byte-wide interface consists of a parity bit (odd parity) a control bit and two 4-bit symbols The DP83257 PLAYERa device has two PHY Port Interfac- es while the DP83256 has one PHY Port Interface Control Bus Interface The Control Bus Interface connects the PLAYERa device to a wide variety of microprocessors and microcontrollers The Control Bus is an asynchronous interface which pro- vides access to 64 8-bit registers which monitor and control the behavior of the PLAYERa device The Control Bus Interface allows a user to Configure SMT features Program the Configuration Switch Enabledisable functions within the Transmitter and Re- ceiver Blocks (ie NRZNRZI Encoder Smoother PHY Request Data Parity Line State Generation Symbol pair Injection NRZNRZI Decoder Cascade Mode etc) The Control Bus Interface also can be used to perform the following functions Monitor Line States received Monitor link errors detected by the Receiver Block Monitor other error conditions Clock Interface The Clock Interface is used to configure the Clock Genera- tion Module and to provide the required clock signals for an FDDI system The following clock signals are generated 5 phase offset 125 MHz Local Byte Clocks 25 MHz Local Symbol Clock 15625 or 3125 MHz System Clock Miscellaneous Interface The Miscellaneous Interface consists of A reset signal User definable sense signals User definable enable signals Synchronization for cascading PLAYERa devices (a high-performance non-FDDI mode) Device Power and Ground pins 6 |
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