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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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AD1980 Arkusz danych(PDF) 5 Page - Analog Devices |
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AD1980 Arkusz danych(HTML) 5 Page - Analog Devices |
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5 / 32 page  REV. 0 AD1980 –5– RESET BIT_CLK SDATA_IN tRST_LOW tRST2CLK tTRI2ACTV tTRI2ACTV Figure 1. Cold Reset Timing (Codec is Supplying the Bit_CLK Signal) SYNC BIT_CLK tSYNC_HIGH tSYNC2CLK Figure 2. Warm Reset Timing BIT_CLK SYNC tCLK_LOW tCLK_HIGH tCLK_PERIOD tSYNC_LOW tSYNC_PERIOD tSYNC_HIGH Figure 3. Clock Timing BIT_CLK SYNC SDATA_IN SDATA_OUT tRISECLK tFALLCLK tRISESYNC tFALLSYNC tRISEDIN tFALLDIN tRISEDOUT tFALLDOUT Figure 4. Signal Rise and Fall Times BIT_CLK SYNC SDATA_IN SDATA_OUT BIT_CLK NOT TO SCALE SLOT 1 SLOT 2 WRITE TO 0 26 DATA PR4 tS2_PDOWN Figure 5. AC-Link Low Power Mode Timing BIT_CL SDATA_O SDATA_I SYN tCO tSETUP VIH VIL VOH VOL tHOLD Figure 6. AC-Link Low Power Mode Timing RESET SDATA_OUT SDATA_IN, BIT_CLK, EAPD, SPDIF_OUT AND DIGITAL I/O Hi-Z tSETUP2RST tOFF Figure 7. ATE Test Mode |
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