STA310 datasheet(16/90 Pages) STMICROELECTRONICS

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STA310

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Table 4.

Figure 7.

Example 2: Only the first 2 bytes are transferred to the STA310 because the number of slots is 20 (16 + 4). SIN

and LRCLKIN are sampled on the falling edge of DSTR. The data is in delayed mode.

The register configuration is SIN_SETUP=3 and CAN_SETUP = DelayMode + LeftFirstChannel + FallingStrobe

+ AllSlot = 1 + 2 + 4 + 8 = 15.

This mode is a specific mode where only the first 16 data bits are transferred. The remaining bits are discarded.

The register configuration is SIN_SETUP = 3 and CAN_SETUP = DelayMode + FallingStrobe = 1 + 4 = 5.

4.4.1.3 SPDIF Input

A true SPDIF Input SPDIF (PCM audio samples) or IEC-61937 (compressed data) is selectable as a main serial

input.

4.4.1.4 Autodetected formats

The STA310 cut 2.0 is able the following audio format changes on the s/pdif input

Table 5. Audio Format detection

When Set

When Clear

Name

Bit 0

The input data is one slot delayed with

respect to LRCLKIN

The input data is not delayed

DelayMode

Bit 1

First channel when LRCLKIN is set

First channel when LRCLKIN is reset

LeftFirstChannel

Bit 2

Data are sampled on falling edge of

DSTR

Data are sampled on rising edge of

DSTR

FallingStrobe

Bit 3

All the bytes are extracted

Only the first 16 data bits are extracted

AllSlot

BEFORE

AFTER

AC3

PCM

AC3

MPEG

AC3

MPEG

PCM

AC3

PCM

MPEG

LRCLKIN

DSTR

SIN

Transferred data

Discarded data

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