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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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TAS3208IPZPR Arkusz danych(PDF) 8 Page - Texas Instruments |
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TAS3208IPZPR Arkusz danych(HTML) 8 Page - Texas Instruments |
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8 / 79 page  SAP OUT (Transmitter ) LRCLKOUT (Recreation / Normalization ) DPLL (11x) DSP_CLK (135 MHz) DIVBY 4 MICRO _CLK (33 MHz) MCLKOUT 256 Fs 2816 Fs 64 Fs Fs SCLKOUT 64Fs SCLKIN LRCLKOUT Fs LRCLKIN MCLKIN 128 Fs MCLKIN DIVBY 2 256 Fs CMS (ClockMaster /SlaveSelection ) DIVBY 2 DIVBY 4 DIVBY 8 DIVBY 512 0 1 0 1 0 1 0 1 CMS CMS SAP IN (Receiver ) SDIN 1 DatatoDSP Ch 1[23 :0 ] ON (OutputNormalization Enable ) SDOUT 1 DatafromDSP Ch 1 [23 :0] SDIN 2 SDIN 3 DatatoDSP Ch 2[23 :0 ] DatatoDSP Ch 3[23 :0 ] DatatoDSP Ch 4[23 :0 ] DatatoDSP Ch 5[23 :0 ] DatatoDSP Ch 6[23 :0 ] DatafromDSP Ch 2 [23 :0] DatafromDSP Ch 3 [23 :0] DatafromDSP Ch 4 [23 :0] sdout 2 SPDIF_CLK IM[1:0] (SAP InputMode ) OM[1 :0]( SAP OutputMode ) SPDIF Transmitter ParallelDatafromDSP SPDIF _ L[23 :0] ParallelDatafromDSP SPDIF _R[23 :0 ] SPDIF _CONTROL _ REG_IN[] spdif _tx_out 01 00 1* SPDIF _IN I2 CModule DIVby 10 DIVby (M+1) DIVby 2^N I2CSamplingClock (N = 0) SCL SDA I2CMasterSCL Clock (M = 8) IM [1:0] DigitalSignalProcessor (DSP) 8051uC & Control N[2:0] M[2:0] CMS IW[1:0] ( SAP InputWordSize ) OW[1 :0]( SAP OutputWordSize ) OUTMUX [1 :0] (AudioOutputSelect - ControlBits [1 :0] fromSPDIFControlRegister : 0x16 ) SPDIF_OUT / SDOUT2 0 1 SPDIF_MUTE 0 (MuteControlRegister : 0x09) SAPOUT _MUTE [1 :0] OSC 512Fs TAS3208 SLES201E – JANUARY 2007 – REVISED MARCH 2011 www.ti.com Clocks The TAS3208 can be configured as either the clock master or clock slave depending on the settings in the clock configuration register. By default, the TAS3208 is configured as the clock master. Figure 3 shows the block diagram of the TAS3208 clocks. Figure 3. Clocking System Digital Audio Interface The TAS3208 has three digital inputs that accept discrete I2S, discrete left-justified, and discrete right-justified PCM data. The TAS3208 has two digital outputs that provide discrete I2S, discrete left-justified, and discrete right-justified PCM data.The second digital output can also be configured to provide SPDIF encoded PCM data. The TAS3208 has a SPDIF input that is capable of routing an SPDIF-encoded signal through the device. This input is not processed by the digital audio processor (DAP). The clocking system for the device is shown in Figure 4. 8 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): TAS3208 |
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