LP8553 datasheet(34/42 Pages) TI1

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LP8553

SNVS701B – SEPTEMBER 2011 – REVISED JANUARY 2014

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EEPROM ADDRESS 5 register

Name

Bit

Access

Description

EN_VSYNC

R/W

Enable VSYNC function

0 = VSYNC input disabled

1 = VSYNC input enabled. VSYNC signal is used by the internal PLL to generate

PWM output and boost frequency.

DITHER

6:5

R/W

Dither function controls

00 = Dither function disabled

01 = 1-bit dither used for output PWM transitions

10 = 2-bit dither used for output PWM transitions

11 = 3-bit dither used for output PWM transitions

VBOOST

4:0

R/W

Boost voltage control from 10V to 40V with 1V step. If adaptive boost control is

enabled, this sets the initial start voltage for the boost converter. If adaptive mode

is disabled, this will directly set the output voltage of the boost converter.

0 0000 = 10V

0 0001 = 11V

0 0010 = 12V

...

1 1101 = 39V

1 1110 = 40V

1 1111 = 40V

EEPROM Address 6

Address A6h

EEPROM ADDRESS 6 register

PLL[12:5]

Name

Bit

Access

Description

PLL

7:0

R/W

13-bit counter value for PLL, 8 MSB bits. PLL[12:0] bits are used when en_vsync =

1. See table below for PLL value calculation.

EEPROM Address 7

Address A7h

EEPROM ADDRESS 7 register

PLL[4:0]

EN_F_RES

HYSTERESIS[1:0]

Name

Bit

Access

Description

PLL

7:3

R/W

13-bit counter value for PLL, 5 LSB bits. PLL[12:0] bits are used when en_vsync = 1. See

table below for PLL value calculation.

EN_F_RES

R/W

Enable PWM output frequency set resistor

0 = Resistor is disabled and PWM output frequency is set with PWM_FREQ EEPROM

1 = PWM frequency set resistor is enabled. RFSET defines the output PWM frequency. See

table in PWM Frequency Setting for full description of the PWM frequencies.

HYSTERESIS

1:0

R/W

PWM input hysteresis function. Will define how small changes in the PWM input are

ignored to remove constant switching between two values.

00 = OFF

01 = 1-bit hysteresis with 11-bit resolution

10 = 1-bit hysteresis with 10-bit resolution

11 = 1-bit hysteresis with 8-bit resolution

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