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DS90CF366 Arkusz danych(PDF) 10 Page - National Semiconductor (TI) |
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DS90CF366 Arkusz danych(HTML) 10 Page - National Semiconductor (TI) |
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10 / 16 page ![]() AC Timing Diagrams (Continued) 10108511 C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos — Transmitter output pulse position (min and max) RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 9) + ISI (Inter-symbol interference) (Note 10) Cable Skew — typically 10 ps–40 ps per foot, media dependent Note 9: Cycle-to-cycle jitter is less than 250 ps at 85 MHz. Note 10: ISI is dependent on interconnect length; may be zero. FIGURE 13. Receiver LVDS Input Skew Margin www.national.com 10 |
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