DS90CF366 datasheet(14/16 Pages) NSC

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Pin Diagrams for TSSOP Packages

DS90CF386MTD

DS90CF366MTD

10108523

10108513

Applications Information

POWER SEQUENCING AND POWERDOWN MODE

Outputs of the transmitter remain in TRI-STATE until the

power supply reaches 2V. Clock and data outputs will begin

to toggle 10 ms after V

CC has reached 3V and the Power-

down pin is above 1.5V. Either device may be placed into a

powerdown mode at any time by asserting the Powerdown

pin (active low). Total power dissipation for each device will

decrease to 5 µW (typical).

The transmitter input clock may be applied prior to powering

up and enabling the transmitter. The transmitter input clock

may also be applied after power up; however, the use of the

PWR DOWN pin is required as described in the Transmitter

Input Clock section. Do not power up and enable (PWR

DOWN = HIGH) the transmitter without a valid clock signal

applied to the TxCLK IN pin.

The FPD Link chipset is designed to protect itself from

accidental loss of power to either the transmitter or receiver.

If power to the transmit board is lost, the receiver clocks

(input and output) stop. The data outputs (RxOUT) retain the

states they were in when the clocks stopped. When the

receiver board loses power, the receiver inputs are con-

trolled by a failsafe bias circuitry. The LVDS inputs are

High-Z during initial power on and power off conditions.

Current is limited (5 mA per input) by the fixed current mode

drivers, thus avoiding the potential for latchup when power-

ing the device.

RECEIVER FAILSAFE FEATURE

The FPD Link receivers have input failsafe bias circuitry to

guarantee a stable receiver output for floating or terminated

receiver inputs. Under these conditions receiver inputs will

be pulled to a HIGH state. This is the case if not all data

channels are required in the application. Leave the extra

channel’s inputs open. This minimizes power dissipation and

locks the unused channels outputs into a stable known

(HIGH) state.

If a clock signal is present, data outputs will all be HIGH; if

the clock input is also floating/terminated, data outputs will

remain in the last valid state. A floating/terminated clock

input will result in a LOW clock output.

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