DP7269

© NIDEC COPAL ELECTRONICS CORP.

5

D

.

v

e

R

3

2

1

2

-

D

M

.

o

N

.

c

o

D

Characteristics subject to change without notice

POWER UP TIMING

(1)(2)

s

t

i

n

U

x

a

M

r

e

t

e

m

a

r

a

P

l

o

b

m

y

S

s

m

1

n

o

i

t

a

r

e

p

O

d

a

e

R

o

t

p

u

-

r

e

w

o

P

s

m

1

n

o

i

t

a

r

e

p

O

e

t

i

r

W

o

t

p

u

-

r

e

w

o

P

DP TIMING

s

t

i

n

U

x

a

M

r

e

t

e

m

a

r

a

P

l

o

b

m

y

S

s

µ

0

1

e

l

b

a

t

S

y

l

p

p

u

S

r

e

w

o

P

r

e

t

f

A

e

m

i

T

e

s

n

o

p

s

e

R

r

e

p

i

W

s

µ

0

1

d

e

u

s

s

I

n

o

i

t

c

u

r

t

s

n

I

r

e

t

f

A

e

m

i

T

e

s

n

o

p

s

e

R

r

e

p

i

W

WRITE CYCLE LIMITS

(3)

s

t

i

n

U

x

a

M

r

e

t

e

m

a

r

a

P

l

o

b

m

y

S

s

m

5

e

m

i

T

e

l

c

y

C

e

t

i

r

W

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Reference Test Method

Min

Max

Units

(1)

Endurance

MIL-STD-883, Test Method 1033

1,000,000

Cycles/Byte

(1)

Data Retention

MIL-STD-883, Test Method 1008

100

Years

(1)

ESD Susceptibility

MIL-STD-883, Test Method 3015

2000

V

(1)

A

m

0

0

1

7

1

d

r

a

d

n

a

t

S

C

E

D

E

J

p

U

-

h

c

t

a

L

Notes:

(1)

This parameter is tested initially and after a design or process change that affects the parameter.

(2)

(3)

The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write

cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.

Figure 1. Bus Timing

tHIGH

SCL

SDA IN

SDA OUT

tLOW

tF

tLOW

tR

tBUF

tSU:STO

tSU:DAT

tHD:DAT

tHD:STA

tSU:STA

tAA

tDH