SC1200 datasheet(39/60 Pages) TI

39 / 60 page

MSC1200

SBAS289E

www.ti.com

Reset Value

SFR A4H

SECIP

SUMIP

ADCIP

MSECIP

I2CIP

CNTIP

ALVDIP

Unused

00H

SECIP

Second System Timer Interrupt Poll (before IRQ masking).

bit 7

0 = Seconds System Timer Interrupt Poll Inactive

1 = Seconds System Timer Interrupt Poll Active

SUMIP

Accumulator Interrupt Poll (before IRQ masking).

bits 6

0 = Accumulator Interrupt Poll Inactive

1 = Accumulator Interrupt Poll Active

ADCIP

ADC Interrupt Poll (before IRQ masking).

bits 5

0 = ADC Interrupt Poll Inactive

1 = ADC Interrupt Poll Active

MSECIP

Millisecond System Timer Interrupt Poll (before IRQ masking).

bits 4

0 = Millisecond System Timer Interrupt Poll Inactive

1 = Millisecond System Timer Interrupt Poll Active

I2CIP

I2C Interrupt Poll (before IRQ masking).

bits 3

0 = I2C Interrupt Poll Inactive

1 = I2C Interrupt Poll Active

CNTIP

Serial Bit Count Interrupt Poll (before IRQ masking).

bits 2

0 = Serial Bit Count Interrupt Poll Inactive

1 = Serial Bit Count Interrupt Poll Active

ALVDIP

Analog Low Voltage Detect Interrupt Poll (before IRQ masking).

bits 1

0 = Analog Low Voltage Detect Interrupt Poll Inactive

1 = Analog Low Voltage Detect Interrupt Poll Active

Auxilliary Interrupt Poll (AIPOL)

Reset Value

SFR 9BH

00H

SPIDATA

SPI Data Register. Data for SPI is read from or written to this location. The SPI transmit and receive buffers

bits 7-0

are separate registers, but both are addressed at this location.

I2CDATA

I2C Data Register. Data for I2C is read from or written to this location. The I2C transmit and receive buffers

bits 7-0

are separate registers, but both are addressed at this location.

SPI Data Register (SPIDATA) / I2C Data Register (I2CDATA)

DCS

Disable Serial Clock Stretch.

bit 1

0: Enable SCL Stretch (cleared by firmware or START condition)

1: Disable SCL Stretch

CNTSEL

Counter Select.

bit 0

0: Counter IRQ Set for Bit Counter = 8 (default)

1: Counter IRQ Set for Bit Counter = 1

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