MCP3913 datasheet(69/82 Pages) MICROCHIP

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 2013 Microchip Technology Inc.

DS20005227A-page 69

MCP3913

8.9

OFFCAL_CHn and GAINCAL_CHn

Registers – Digital Offset and Gain

Error Calibration Registers

Name

Bits

Address

Cof.

OFFCAL_CH0

0x0F

R/W

GAINCAL_CH0

0x10

R/W

OFFCAL_CH1

0x11

R/W

GAINCAL_CH1

0x12

R/W

OFFCAL_CH2

0x13

R/W

GAINCAL_CH2

0x14

R/W

OFFCAL_CH3

0x15

R/W

GAINCAL_CH3

0x16

R/W

OFFCAL_CH4

0x17

R/W

GAINCAL_CH4

0x18

R/W

OFFCAL_CH5

0x19

R/W

GAINCAL_CH5

0x1A

R/W

OFFCAL_CHN REGISTERS

R/W-0

...

R/W-0

OFF-

CAL_CHn<23>

OFF-

CAL_CHn<22>

OFF-

CAL_CHn<21>

...

OFF-

CAL_CHn<3>

OFF-

CAL_CHn<2>

OFF-

CAL_CHn<1>

OFF-

CAL_CHn<0>

bit 23

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 23-0

OFFCAL_CHn:

Digital Offset calibration value for the corresponding channel CHn. This register is

simply added to the output code of the channel bit-by-bit. This register is 24-bit two's complement

MSB first coding. CHn Output Code = OFFCAL_CHn + ADC CHn Output Code. This register is a

Don't Care if EN_OFFCAL = 0 (Offset calibration disabled), but its value is not cleared by the

EN_OFFCAL bit.

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