CS8401 datasheet(22/34 Pages) ETC

22 / 34 page

When FSYNC is a word clock (Format 2), CBL

is sampled when left C,U,V are sampled. When

FSYNC is Left/Right, CBL is sampled when left

C,U,V are sampled. The channel status block

boundary is reset when CBL transitions from

low to high (based on two successive samples of

CBL). MCK for the CS8402A is normally ex-

pected to be 128 times the sample frequency, in

the transparent mode MCK must be 256 Fs.

Professional Mode

Setting PRO low places the CS8402A in profes-

sio na l mo de a s show n in Figu re 19. In

professional mode, channel status bit 0 is trans-

mitted as a one and bits 1, 2, 3, 4, 6, 7, and 9

can be controlled via dedicated pins. The pins

are actually the inverse of the identified bit. For

example, tying the C1 pin low places a one in

channel status bit 1. As shown in the Application

Note, Overview of AES/EBU Digital Audio In-

t e rfac e

D at a

S t ru ct u re s ,

C 1

i ndicat es

audio/non-audio; C6 and C7 determine the sam-

ple frequency; and C9 allows the encoded

channel mode to be stereophonic. EM1 and EM0

determine emphasis and encode C2, C3, C4 as

shown in Table 4. The dedicated channel status

pins are read at the appropriate time and are

logically OR’ed with data input on the channel

status port, C. In Transparent Mode, these dedi-

cated channel status pins are ignored; and

channel status bits are input at the C pin.

The channel status data cyclic redundancy check

character (C.S. byte 23) is always generated in-

dependently for channels A and B and is

transmitted at the end of the channel status

block.

Data should not be input through the channel status

port, C, during the CRCC byte time frame, since in-

puts on C are logically OR’ed with internally

generated data.

Consumer Mode

Setting PRO high places the CS8402A in consumer

mode which redefines the pins as shown in Fig-

ure 20. In consumer mode, channel status bit 0 is

transmitted as a zero and channel status bits 2, 3, 8,

9, 15, 24, and 25 are controlled via dedicated pins.

The pins are actually the inverse of the bit so if pin

Parity

Preamble

Timing

Mux

MCK

TXP

TXN

Serial

Port

Audio

Logic

FSYNC

SCK

SDATA

C Bits

Aux

Biphase

Mark

Encoder

Line

Driver

RST

CBL

EM1

EM0

PRO

Registers

U Bits

Validity

CRC

TRNPT

Figure 19. CS8402A Block Diagram - Professional Mode

CS8402A

DS60F1

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