CS8401 datasheet(20/34 Pages) ETC

20 / 34 page

C, U, V Serial Port

The serial input pins for channel status (C), user

(U), and validity (V) are sampled during the first

bit period after the active edge of FSYNC for all

formats except Format 4, which is sampled dur-

ing the second bit period (coincident with the

MSB). In Figure 16, the arrows on SCK indicate

when the C, U, and V bits are sampled. The C,

U, and V bits are transmitted with the audio

sample entered before the FSYNC edge that

sampled it. The V bit, as defined in the audio

standards, is set to zero to indicate the audio data

is suitable for conversion to analog. Therefore,

when the audio data is errorred, or the data is

not audio, the V bit should be set high. The

channel status serial input pin (C) is not avail-

able in consumer mode when the CD subcode

port is enabled (FC1 = FC0 = high). Any chan-

nel status data entered through the channel status

serial input (C) is logically OR’ed with the data

entered through the dedicated pins or internally

generated.

RST and CBL (TRNPT is low)

When RST goes low, the differential line drivers

are set to ground and the block counters are reset

to the beginning of the first block. In order to

properly synchronize the CS8402A to the audio

serial port, the transmit timing counters, which

include CBL, are not enabled after RST goes

high until eight and one half SCK periods after

the active edge (first edge after reset is exited) of

FSYNC. When FSYNC is configured as a

left/right signal (all defined formats except 2),

the counters and CBL are not enabled until the

right sample is being entered (during which the

previous left sample is being transmitted). This

guarantees that channel A is left and channel B

is right as per the digital audio interface specs.

As shown in Figure 17, CBL, channel block start

output, can assist in serially inputting the C, U

and V bits as CBL goes high one bit period be-

fore the first bit of the preamble of the first

sub-frame of the channel status block is trans-

CUV0L

CUV0R

CUVIL

Left 0

Preamble Z

VUCP0L

Right 0

Preamble Y

VUCP0R

Right 191

Preamble Y

VUCP191R

SDATA

C,U,V

FSYNC

TXP

TXN

CUV128R

Left 128

Preamble X

VUCP128L

VUCP127R

CUV1R

C bit OR'ed w/

C1 pin

CUV0L

CUV0R

Preamble Y

Right 128

Left 0

Left 1

Right 0

Right 128

Left 0

Left 128

C bits OR'ed w/

PRO pin

CUV191R

CUV0L

CUV0R

CUV1L

CUV191R

CUV0L

TRNPT high

TRNPT low

Bit 0 of C.S.

Block Byte 16

CBL

Aux Data

03 4

LSB

Left 0 - Audio Data

Preamble Z

28 29 30 31

MSB

bit

Sub-frame

TRNPT high

TRNPT low

C bits from Cpin

CUV128L

Figure 17. CBL and Transmitter Timing

CS8402A

DS60F1

CS8401 Arkusz danych(PDF) 20 Page - List of Unclassifed Manufacturers

CS8401 Arkusz danych(HTML) 20 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Arkusz danych Pobierz

Link URL