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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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STM32F427AI Arkusz danych(PDF) 97 Page - STMicroelectronics |
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STM32F427AI Arkusz danych(HTML) 97 Page - STMicroelectronics |
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97 / 239 page  DocID024030 Rev 9 97/238 STM32F427xx STM32F429xx Electrical characteristics 197 6.3.3 Operating conditions at power-up / power-down (regulator ON) Subject to general operating conditions for TA. Table 20. Operating conditions at power-up / power-down (regulator ON) 6.3.4 Operating conditions at power-up / power-down (regulator OFF) Subject to general operating conditions for TA. Symbol Parameter Min Max Unit tVDD VDD rise time rate 20 ∞ µs/V VDD fall time rate 20 ∞ Table 21. Operating conditions at power-up / power-down (regulator OFF)(1) 1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below 1.08 V. Symbol Parameter Conditions Min Max Unit tVDD VDD rise time rate Power-up 20 ∞ µs/V VDD fall time rate Power-down 20 ∞ tVCAP VCAP_1 and VCAP_2 rise time rate Power-up 20 ∞ VCAP_1 and VCAP_2 fall time rate Power-down 20 ∞ |
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