BL24C64A 64Kbits (8,192×8)

BL24C64A 64Kbits (8,192×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited

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3. Device Addressing

The 64K EEPROM devices all require an 8-bit device address word following a start condition to enable

the chip for a read or write operation (see Figure 5)

The device address word consists of a mandatory "1", "0" sequence for the first four most significant

bits as shown. This is common to all the Serial EEPROM devices.

The 64K EEPROM uses A2, A1 and A0 device address bits to allow as much as eight devices on the same

bus. These 3 bits must be compared to their corresponding hardwired input pins. The A2, A1 and A0

pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed

to float.

The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if

this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the

chip will return to a standby state.

DATA SECURITY:

The BL24C64A has a hardware data protection scheme that allows the user to write

protect the entire memory when the WP pin is at VCC.

4. Write Operations

BYTE WRITE:

A write operation requires an 8-bit data word address following the device address word

and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then

clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0"

and the addressing device, such as a microcontroller, must terminate the write sequence with a stop

condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile

memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write

is complete (see Figure 6).

PAGE WRITE:

A write operation requires an 8-bit data word address following the device address word

and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then

clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0"

and the addressing device, such as a microcontroller, must terminate the write sequence with a stop

condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile

memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write

is complete (see Figure 7).

The data word address lower five bits are internally incremented following the receipt of each data

word. The higher data word address bits are not incremented, retaining the memory page row location.

When the word address, internally generated, reaches the page boundary, the following byte is placed

at the beginning of the same page. If more than 32 data words are transmitted to the EEPROM, the

WRITE IDENTIFICATION PAGE:

The Identification Page (32 bytes) is an additional page which can be

written and (later) permanently locked in Read-only mode. It is written by issuing the Write