ADL5205ACPZ-R7 datasheet(21/32 Pages) AD

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ADL5205

Data Sheet

Rev. 0 | Page 20 of 31

Table 9. Gain Code vs. Voltage Gain

6-Bit Binary Gain Code, D5 to D0

Voltage Gain (dB)

000000

+26

000001

+25

000010

+24

000011

+23

000100

+22

000101

+21

000110

+20

000111

+19

001000

+18

001001

+17

001010

+16

001011

+15

001100

+14

001101

+13

001110

+12

001111

+11

010000

+10

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

−1

011100

−2

011101

−3

011110

−4

011111

−5

100000

−6

100001

−7

100010

−8

100011 to 111111

−9

SPI READ

The ADL5205 can be read back only in the serial mode, during

a read cycle (from CSA/CSB low to CSA/CSB high) after the

R/W bit is set high in the previous cycle. During the read cycle,

data changes at each rising edge of SCLK, and can be latched

using the falling edge of SCLK. There is no continual read opera-

tion. A logic high (1) must be written into the R/W bit to enable

the subsequent read cycle. The sequence for reading back is

shown in Figure 54 to Figure 57, showing the operation of the

input and output functions of the SDIO pin. The actual

waveforms during the readback process are shown in Figure 57

to Figure 59. SDIO is enabled as an output only during the read

cycle in Figure 57.

SCLK

WRITE VALUE

WRITE 0x0054

R/W BIT LOW ON SDIO_IN

DATA WRITTEN ON RISING CLOCK EDGE

CSA, CSB

SDIO (IN)

SDIO (OUT)

Figure 54. Write Gain Control Word

SCLK

SET UP READ

WRITE 0x0100

R/W BIT LOW ON SDIO_OUT

CSA, CSB

SDIO (IN)

SDIO (OUT)

Figure 55. Write Logic 1 into R/W Bit

SCLK

SDIO (IN)

SDIO (OUT)

PERFORM READ

READ 0x0154

R/W BIT HIGH

DATA READ ON FALLING CLOCK EDGE

CSA, CSB

SDIO OUTPUT ENABLED

Figure 56. Perform Read

CH1 1V/DIV

CH2 1V/DIV

A CH2

1.6V

CH3 1V/DIV

SCLK

SDIO

CSA OR CSB

Figure 57. Write Gain Control Value, 0x0054

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