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SC1403 Arkusz danych(PDF) 20 Page - Semtech Corporation |
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SC1403 Arkusz danych(HTML) 20 Page - Semtech Corporation |
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20 / 30 page ![]() 20 2002 Semtech Corp. www.semtech.com SC1403 PRELIMINARY POWER MANAGEMENT PRELIMINARY Ic a p Iin averag e 0 0 I3 in I5 in As the input voltage is reduced, the duty cycle of both converters increases. For inputs less than 8.3 volts it is impossible to prevent overlap when producing 3.3V and 5V outputs, regardless of the phase relationship between the converters. This can be seen in the following figure. I3 in I5 in Iin 0 averag e Ic a p 0 pe riod ph ase lea d From an input filter standpoint it is desirable to make the minimize the overlap, but it is also desirable to keep the turn-on and turn-off transitions of the two converters separated in time, otherwise the two converters may affect each other due to switching noise. The SC1403 implements this by changing the phase relationship between the converter depending on the input voltage. e g a tl o v t u p n Ig n i s ir r e t r e v n o c V 3 m o r f d a e l e s a h P e g d e g n i s ir r e t r e v n o c V 5 o t e g d e V 6 . 9 > n i Vd o ir e p g n i h c ti w s f o % 1 4 V 7 . 6 > n i V > V 6 . 9d o ir e p g n i h c ti w s f o % 9 5 n i V > 7 . 6d o ir e p g n i h c ti w s f o % 4 6 Vin > 9.6V: 3.3V turn-on leads 5V turn-on by 41% of the switching period. With Vin > 9.6V it is always possible to achieve no overlap, which minimizes the input ripple current. At Vin = 9.6V there is no overlap, but the 3.3V turn-on is nearing the 5V turn-off converter. 6.7 < Vin < 9.6V: 3.3V turn-on leads 5V turn-on by 59% of the period. To prevent the 3V turn-on from coinciding with the 5V turn- off (which could affect either output), the 5V pulse is delayed in time slightly such that the 3V turn-on occurs before the 5V turn-off. This creates a small overlap between the 3V turn-on and the 5V turn-off, with a resulting slight increase in RMS input ripple, but this is preferred since it greatly reduces noise problems caused by simultaneous transitions. Note that at Vin = 6.7, the 3V turn-off is nearing the 5V turn-on. Vin < 6.7 volts: 3.3V turn-on leads 5V turn-on by 64% of the period. The 5V turn-on is delayed slightly more to add separation between the 3V turn-off and 5V turn-on. This leads to more overlap, but at this point overlap is unavoidable. Input ripple current calculations: The following equations provide quick approximations for input ripple current: D3 = 3.3V duty cycle = 3.3/Vin D5 = 5V duty cycle = 5/Vin I3 = 3.3V load current I5 = 5V load current Dovl = overlapping duty cycle of the 3V and 5V pulses, which varies according to input voltage: Vin > 9.6V: Dovl = 0 9.6V > Vin > 6.7V: Dovl = D5 - 0.41 6.7V > Vin Dovl = D5 - 0.36 Irms_cap = Isw_rms2 Iin2 + Iin = D3 . I3 + D5 . I5 (average current drawn from Vin) Isw_rms = rms current flowing into 3V and 5V SMPS (Isw_rms)2 = Dovl . (I3 + I5)2 + (D3 - Dovl) . I32 + (D5 -Dovl) . I52 The worst-case ripple current varies by application. For the case of I3 = I5 = 6A, the worst-case ripple occurs at Vin = 7.5V, at which point the rms capacitor ripple current is 4.2 amps. To handle this the reference design uses 4 paralleled ceramic capacitors, (Murata GRM32NF51E106Z, 10 uF 25V, size 1210). Each capacitor is rated at 2.2 Amps, allowing for derating at higher temperatures. Out-of-phase Switching |
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