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WM8753LEB/V Arkusz danych(PDF) 13 Page - Wolfson Microelectronics plc |
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WM8753LEB/V Arkusz danych(HTML) 13 Page - Wolfson Microelectronics plc |
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13 / 87 page ![]() WM8753L Advanced Information w AI Rev 3.1 June 2004 13 SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLK t MCLKL t MCLKH t MCLKY Figure 1 System Clock Timing Requirements Test Conditions CLKDIV2=0, DCVDD = 1.42V, DBVDD = AVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, TA = +25 oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT System Clock Timing Information MCLK System clock cycle time TMCLKY 54 ns MCLK duty cycle TMCLKDS 60:40 40:60 Test Conditions CLKDIV2=1, DCVDD = 1.42V, DBVDD = AVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, TA = +25 oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT System Clock Timing Information MCLK System clock pulse width high TMCLKL 10 ns MCLK System clock pulse width low TMCLKH 10 ns MCLK System clock cycle time TMCLKY 27 ns MODE/GPIO3 AND CSB/GPIO5 LATCH ON POWERUP TIMING MODE/GPIO3 AVDD/DCVDD Power-on-Reset (internal) CSB/GPIO5 t puhold t pusetup DBVDD t dbpu |
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