PC97307VUL datasheet(45/218 Pages) NSC

45 / 218 page

Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)

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Note:

The EN FLAGS command (used for routing OBF and

IBF onto P24 and P25 in the 8042) causes unpredict-

able results and should not be issued.

3.3.3

KBC Clock

The KBC clock frequency is selected by the SuperI/O KBC

Configuration Register at index F0h of logical device 0 to be

either 8, 12 or 16 MHz. 16 MHz is not available when the

clock source on pin X1 is 24 MHz. This clock is generated

from a 32.768 KHz crystal connected to pins X1C and X2C,

or from either a 24 MHz or a 48 MHz clock input at pin X1.

See “SuperI/O KBC Configuration Register, Index F0h” on

page 36, Figures 3-4 and 3-5. The clock source and fre-

quency may only be changed when the KBC is disabled.

For details regarding the configuration of each device, refer

to Tables 2-12 and 2-13 starting on page 30.

FIGURE 3-5. External Clock Connection

PC87307/PC97307

+VCC

External

Clock

Standard or

Open-Collector

TTL Driver

FIGURE 3-3. Interrupt Request Logic

FIGURE 3-4. Instruction Timing

From Mouse IRQ

A15-0

AEN

Address

Decoder

Port 60

Read

Mouse IRQ Feedback

From KBC IRQ

CLR

“1”

MUX

Interrupt

KBC IRQ Feedback

CLK

Interrupt Enable

A15-0

AEN

Address

Decoder

Port 60

Read

Interrupt Enable

(1 = Latch)

Interrupt

(0 = Invert)

Type

Polarity

1 MUX

Plug and

Play Matrix

CLR

“1”

MUX

Interrupt

CLK

(1 = Latch)

Interrupt

(0 = Invert)

Type

Polarity

1 MUX

Plug and

Play Matrix

1 Instruction Cycle = 15 Clock Cycles

KBC CLK

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