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VV5404 Arkusz danych(PDF) 36 Page - STMicroelectronics |
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VV5404 Arkusz danych(HTML) 36 Page - STMicroelectronics |
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36 / 54 page ![]() VV5404 & VV6404 CD5404-6404F-A 36/54 Notes: 1. The enable signal enabling the external ADC functionality is the logical OR of CR0[0] bit and the invert of the ADCVDD pin. 2. The low-power select signal for the analogue circuitry is the logical OR of PD0[0] and Setup0[0]. Register Index Bits Function Default Comment 010_00002 7:0 Fine MSB exposure value 0 Maximum mode dependent: 360 (30fps) / 438 (25 fps) 010_00012 7:0 Fine LSB exposure value 010_00102 7:0 Coarse MSB exposure value 302 Maximum: 302 010_00112 7:0 Coarse LSB exposure value 010_01002 2:0 Gain value 0 000: Gain = 1 001: Gain = 2 011: Gain = 4 111: Gain = 8 010_01012 1:0 Clock divisor value 0 00: Pixel clock = CLKI clock/2 01: Pixel clock = CLKI clock/4 10: Pixel clock = CLKI clock/8 11: Pixel clock = CLKI clock/16 Table 24 : Exposure, Clock Rate and Gain Registers Bit Function Default Comment 0 Standby Off/On 0 Powers down ALL analogue circuitry 1 Power Down - ADC Off/On 0 2 Power Down - ADC Top Reference Off/On 0 5:3 Reserved 7:6 Unused Table 25 : Control Register CR [111_01102] |
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