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VV5404 Arkusz danych(PDF) 41 Page - STMicroelectronics |
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VV5404 Arkusz danych(HTML) 41 Page - STMicroelectronics |
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41 / 54 page ![]() VV5404 & VV6404 CD5404-6404F-A 41/54 5.7 Serial Interface Timing NOTE 1: With 200pF capacitive load. It is recommended that pull-up resistors of 2.2k - 4.7k are fitted to both SDA and SCL lines. Parameter Symbol Min. Max. Unit SCL clock frequency fscl 0 100 kHz Bus free time between a stop and a start tbuf 2 - us Hold time for a repeated start thd;sta 80 - us LOW period of SCL tlow 320 - us HIGH period of SCL thigh 160 - us Set-up time for a repeated start tsu;sta 80 - us Data hold time thd;dat 0 - us Data Set-up time tsu;dat 0 - ns Rise time of SCL, SDA tr - 300 (note1) ns Fall time of SCL, SDA tf - 300 (note1) ns Set-up time for a stop tsu;sto 80 - us Capacitive load of each bus line (SCL, SDA) Cb - 200 pF Table 27 : Serial Interface Timing Characteristics SDA SCL thd;sta tr thigh tf tsu;dat thd;dat tsu;sta tsu;sto ... ... thd;sta tlow tbuf stop start stop start all values referred to the minimum input level (high) = 3.5V, and maximum input level (low) = 1.5V Figure 26 : Serial Interface Timing Characteristics |
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