ST1S50 datasheet(20/29 Pages) STMICROELECTRONICS

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Application information

ST1S50

20/29

DocID025723 Rev 4

6.5.2

CSS value

When the EN_SS pin is tied to ground the device is disabled. When the EN_SS is released

a current is a source in the soft-start capacitor connected to the pin. No minimum soft-start

time is assured in case of no capacitor connected.

The FB voltage starts to rise when the EN/SS voltage is equal to 0.7 V (typ.), start threshold,

and reaches the VREFvoltage when the EN/SS voltage is equal to 1.5 V (typ.), stop

threshold.

Considering the 4.7 M

 resistor value (see Section 6.5.1), the soft-start capacitor can be

determined by:

Equation 25

Where TSS is the target soft-start time.

A delay can be observed from EN_SS release and the real VOUT rising since the EN_SS

voltage needs to ramp from zero to the enable threshold (340 mV) with a pull-up current of

350 nA. The delay results:

Equation 26

6.6

Thermal dissipation

The thermal design is important to prevent the thermal shutdown of the device if junction

temperature goes above 150 °C. The three different sources of losses within the device are:

conduction losses due to ON resistance of the high-side switch (RHS) and low-side

switch (RLS); these are equal to:

Equation 27

Where D is the duty cycle of the application. Note that the duty cycle is theoretically given by

the ratio between the VOUT and VIN, but actually it is slightly higher to compensate the

losses of the regulator.

switching losses due to the high-side power MOSFET turn ON and OFF; these

can be calculated as:

Equation 28

Where TRISE and TFALL are the overlap times of the voltage across the high-side power

switch (VDS) and the current flowing into it during turn ON and turn OFF phases, as shown

in Figure 10. TSW is the equivalent switching time. For this device the typical value for the

equivalent switching time is 20 ns.

CSS F



TSS s



154873

--------------------

tDELAY

0.340V C



350nA

-----------------------------------

PCOND

RHS IOUT

2 DR

LS IOUT

–





PSW

VIN IOUT

TRISE TFALL



------------------------------------------- Fsw





VIN IOUT TSW FSW





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