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ST7FOXU0 Arkusz danych(PDF) 49 Page - STMicroelectronics |
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ST7FOXU0 Arkusz danych(HTML) 49 Page - STMicroelectronics |
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49 / 123 page  ST7FOXU0 Power saving modes 49/123 Figure 19. Wait mode flowchart 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. 8.4 Active-halt and halt modes Active-Halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active- Halt or Halt mode is given by the LTCSR/ATCSR register status as shown in the following table: WFI INSTRUCTION RESET INTERRUPT Y N N Y CPU OSCILLATOR PERIPHERALS IBIT ON ON 0 OFF FETCH RESET VECTOR OR SERVICE INTERRUPT CPU OSCILLATOR PERIPHERALS IBIT ON OFF 0 ON CPU OSCILLATOR PERIPHERALS IBIT ON ON X 1) ON 256 CPU CLOCK CYCLE DELAY Table 12. Enabling/disabling active-halt and halt modes LTCSR TBIE bit ATCSR OVFIE bit ATCSRCK1 bit ATCSRCK0 bit Meaning 0x x0 Active-Halt mode disabled 00 x x 0111 1 xxx Active-Halt mode enabled x 101 |
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