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STM32F732ICK6 Arkusz danych(PDF) 24 Page - STMicroelectronics

Numer części STM32F732ICK6
Szczegółowy opis  Dual mode Quad-SPI
PDF  122 Pages
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Producent  STMICROELECTRONICS [STMicroelectronics]
Strona internetowa  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F732ICK6 Arkusz danych(HTML) 24 Page - STMicroelectronics

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Functional overview
STM32F732xx STM32F733xx
24/122
DocID028480 Rev 1
On the STM32F7x3xx devices, the USB OTG HS sub-system uses an additional power
supply pin:
•
The VDD12OTGHS pin is the output of PHY HS regulator (1.2V). An external capacitor
of 2.2 µF must be connected on the VDD12OTGHS pin.
2.15
Power supply supervisor
2.15.1
Internal reset ON
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other packages, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default BOR
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes. The device remains in reset mode when VDD is below a specified threshold,
VPOR/PDR or VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
2.15.2
Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor VDD and NRST and should maintain
the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be
connected to VSS. Refer to Figure 9: Power supply supervisor interconnection with internal
reset OFF.



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