LT4220IGN datasheet(8/16 Pages) LINER

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LT4220

4220f

PI FU CTIO S

FAULT pin to the ON+ pin, otherwise the part remains

latched off.

To disable the timeout circuit breaker, connect the TIMER

pin to GND.

GND (Pin 9): Supply Ground Pin.

PWRGD (Pin 10): Open-Collector Output to GND. PWRGD

goes to high impedance after the initial GATE– and final

GATE+ pins have reached their maximum voltage and after

the FB+ pin goes above 1.24V low-to-high threshold and

after the FB– pin falls below –1.24V high-to-low threshold.

An external pull-up resistor can pull the pin to a voltage

higher or lower than VCC. If not used, PWRGD can be left

floating or tied to GND.

FAULT (Pin 11): Open-Collector Output to GND. The

FAULT pin is pulled low whenever the TIMER pin rises

above VTIMERH (1.24V) threshold, thereby setting the

internal fault latch. It goes to high impedance whenever the

internal fault latch is reset. The fault latch is reset with

either internal undervoltage lockout conditions, or by the

ON comparators if the TIMER pin is also below 0.5V. If not

used, the FAULT pin can be left floating or tied to GND.

ON+ (Pin 12): Positive Supply Good Comparator Input. It

monitors the positive input voltage (VCC) with an external

resistive divider for undervoltage lockout. When the volt-

age on ON+ is above the VON+H high-to-low threshold

(1.24V) the positive supply is considered good. If ON+

drops below 1.185V, both GATE– and GATE+ are pulled

low.

If ON+ is pulled low after a current limit fault and when the

TIMER pin is below 0.5V, the fault latch is reset allowing

the part to turn back on. Typically the FAULT pin is tied

back to the ON+ pin for autorestart. If not used, the ON+ pin

should be set to a voltage in the range of 1.3V < ON+ < VCC

+ 0.3V. The ON+ pin requires a bypass capacitor connected

to ground.

FB+ (Pin 13): Positive Power Good Comparator Input. This

pin monitors the positive output voltage (VOUT+) with an

external resistor divider. When the voltage on FB+ is above

the VFB+H low-to-high threshold (1.24V) and the GATE+

drive voltage has reached a maximum, the PWRGD is

released. PWRGD is pulled low when the FB+ pin is below

1.185V. The PWRGD pin is wire-ORed with the FB– pin

conditions.

FB+ also controls the positive current limit sense amplifier

input offset to provide foldback current limit. The FB+ pin

linearly reduces the positive sense amplifier offset from

48mV to 15mV for FB+ in the range 0.85V > FB+ > 0V. If

PWRGD and foldback current limit are not used, the FB+

pin should be set to a voltage in the range of 1.3V < FB+ <

VCC + 0.3V.

GATE+ (Pin 14): High Side Gate Drive for the External

Positive Supply N-Channel FET. An internal charge pump

guarantees at least 3.5V above VCC, for supply voltages at

±2.7Vincreasingtoaminimumof5VaboveVCCforsupply

voltages greater than

±5V. A 10µA pull-up current source

drives the pin. An external capacitor connected from the

GATE+ pin to GND will control the rising slope of the GATE+

signal. The voltage is clamped to 7V above VCC.

When the current limit is reached, the GATE+ pin voltage

will be adjusted to maintain a constant voltage across the

RS+ resistor while the timer capacitor starts to charge. If

the TIMER pin voltage exceeds 1.24V, the GATE+ pin will

be pulled low.

The GATE+ pin is pulled to GND whenever the ON+ pin is

below 1.24V, the ON– pin is above –1.24V, either supply is

in the undervoltage lockout voltage range, or the TIMER

pin rises above 1.24V.

SENSE+ (Pin 15): Positive Supply Current Limit Sense Pin.

A sense resistor must be placed in the supply path be-

tween VCC and SENSE+. The current limit circuit will

regulate the voltage across the sense resistor to 50mV

(VCC – SENSE+) when the FB+ voltage is greater than

0.85V. If VFB+ goes below 0.85V, the voltage across the

sense resistor decreases linearly and stops at 15mV when

VFB+ is 0V.

VCC (Pin 16): Positive Supply. The positive supply input

ranges from 2.7V to 16.5V for normal operation. ICC is

typically 2.7mA. An internal undervoltage lockout circuit

disables the chip for inputs less than 2.45V. Place a 0.1

µF

bypass capacitor next to the VCC pin.

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