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MPC823 Arkusz danych(PDF) 65 Page - Freescale Semiconductor, Inc |
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MPC823 Arkusz danych(HTML) 65 Page - Freescale Semiconductor, Inc |
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65 / 70 page ![]() MPC823 ELECTRICAL SPECIFICATIONS 65 Tcyc is the cycle time of the LCD clock (shift clock). Tdelay is a circuit delay that is specified in the AC electrical specifications. 1Ð16 lines is a time period that can vary between one scan line and 16, depending on how the LCD controller is programmed in the VPW field of the LCVCR. 0Ð1,023 lines is a time period that can vary between 0 and 1,023 scan lines in the WBF field of the LCVCR. Table 21. LCD Controller Timing NUM CHARACTERISTIC 25MHZ 40MHZ 50MHZ UNIT MIN MAX MIN MAX MIN MAX 220 Shift clock cycle time 40 Ñ 40 Ñ 40 Ñ nsec 221 Shift clock high time 20 Ñ 20 Ñ 20 Ñ nsec 223 CLOCK/HSYNC/VSYNC/OE rise and fall times Ñ 10 Ñ 10 Ñ 10 nsec 224 Data valid delay from shift clock high Ñ 15 Ñ 15 Ñ 15 nsec 225 VSYNC to HSYNC setup time1 5Ñ5Ñ5Ñ T 226 VSYNC hold time 1Ñ1Ñ1Ñ T 227 HSYNC pulse width 4Ñ4Ñ4Ñ T 228 Time from clock falling edge to HSYNC rising edge 4.5 Ñ 4.5 Ñ 4.5 Ñ T 229 Time from HSYNC falling edge to clock rising edge2 4Ñ4Ñ4Ñ T 230 AC active delay Ñ 25 Ñ 25 Ñ 25 nsec 231 VSYNC pulse width (TFT) 1 16 1 16 1 16 Line 232 HSYNC to OE delay3 4Ñ4Ñ4Ñ T 233 OE to HSYNC delay 4Ñ4Ñ4Ñ T 234 VSYNC to OE delay (TFT) 0 1,023 0 1,023 0 1,023 T 235 VSYNC/HSYNC/OE active delay (TFT) Ñ 15 Ñ 15 Ñ 15 nsec 236 Wait between frames4 WBF Ñ WBF Ñ WBF Ñ Line NOTES: 1. T = shift clock cycle (220). 2. This number is given for wbl(wait between lines) £ 2. For wbl=n {n>2} the timing will be (n+2)T. 3. This number is given for wbl(wait between lines) £ 2. For wbl=n {n>2} the timing will be (n+2)T. 4. Wait Between Frames (WBF) is a programmable parameter. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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