TAS3001CPWR datasheet(48/56 Pages) TI

48 / 56 page

A−2

A.1 Main Control Register (MCR)

Configuration of the digital serial audio interface is set up through the main control register as shown in Table A−2

and Table A−3. Bits F0 and F1 allow selection between three different serial data formats (left justified = 00, right

justified = 01, and I2S standard = 10). The output serial port mode set by E0 and E1 must be set to the same value

as the input serial port mode set by F0 and F1. Bits W0 and W1 allow selection between three different word widths

(16-bit word = 00, 18-bit word = 01, and 20-bit word = 10). The SC bit selects 32fs (0) or 64fs (1) bit clock. The FL

bit is primarily for use during initialization and is defined in Device Initialization (see Section 5.1). See Section 3, Serial

Control Interface, for additional information on how to address the main control register.

Table A−2. Main Control Register (MCR)

Table A−3. Main Control Register (MCR) Description

BIT

DESCRIPTOR

FUNCTION

VALUE

FUNCTION

C(7)

Fast load

Normal operating mode

C(7)

Fast load

1 (default)

Fast load mode

C(6)

SCLK frequency

SCLK = 32

× fs

C(6)

SCLK frequency

SCLK = 64

× fs

C(5,4)

E(1,0)

Output serial port mode

Left justified

C(5,4)

E(1,0)

Output serial port mode

Right justified

I2S

Reserved

C(3,2)

F(1,0)

Input serial port mode

Left justified

C(3,2)

F(1,0)

Input serial port mode

Right justified

I2S

Reserved

C(1,0)

W(1,0)

Serial port word length

16 bit

C(1,0)

W(1,0)

Serial port word length

18 bit

20 bit

Reserved

TAS3001CPWR Arkusz danych(PDF) 48 Page - Texas Instruments

TAS3001CPWR Arkusz danych(HTML) 48 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Arkusz danych Pobierz

Link URL