AD9683 datasheet(9/45 Pages) AD

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AD9683

Data Sheet

Rev. D | Page 8 of 44

SWITCHING SPECIFICATIONS

Table 4.

AD9683-170

AD9683-250

Parameter

Symbol

Temperature

Min

Typ

Max

Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Conversion Rate1

Full

170

250

MSPS

SYSREF± Setup Time to Rising Edge CLK±2

tREFS

Full

300

SYSREF± Hold Time from Rising Edge CLK±2

tREFH

Full

SYSREF± Setup Time to Rising Edge RFCLK±2

tREFSRF

Full

400

SYSREF± Hold Time from Rising Edge RFCLK±2

tREFHRF

Full

CLK± Pulse Width High

tCH

Divide-by-1 Mode, DCS Enabled

Full

2.61

2.9

3.19

1.8

2.0

2.2

Divide-by-1 Mode, DCS Disabled

Full

2.76

2.9

3.05

1.9

2.0

2.1

Divide-by-2 Mode Through Divide-by-8 Mode

Full

0.8

Aperture Delay

Full

1.0

Aperture Uncertainty (Jitter)

Full

0.16

ps rms

DATA OUTPUT PARAMETERS

Data Output Period or Unit Interval (UI)

Full

20 × fS

Seconds

Data Output Duty Cycle

25°C

Data Valid Time

25°C

0.82

0.78

PLL Lock Time

tLOCK

25°C

µs

Wake-Up Time

Standby

25°C

µs

ADC (Power-Down)3

25°C

250

µs

Output (Power-Down)4

25°C

µs

Subclass 0: SYNCINB± Falling Edge to First Valid

K.28 Characters (Delay Required for Rx CGS Start)

Full

Multiframes

Subclass 1: SYSREF± Rising Edge to First Valid K.28

Characters (Delay Required for SYNCINB± Rising

Edge/Rx CGS Start)

Full

Multiframes

CGS Phase K.28 Characters Duration

Full

Multiframe

Pipeline Delay

JESD204B (Latency)

Full

Cycles5

Fast Detect (Latency)

Full

Cycles5

Lane Rate

Full

3.4

Gbps

Uncorrelated Bounded High Probability (UBHP) Jitter

Full

Random Jitter

At 3.4 Gbps

Full

2.4

ps rms

At 5 Gbps

Full

1.7

ps rms

Output Rise/Fall Time

Full

Differential Termination Resistance

25°C

100

Ω

Out-of-Range Recovery Time

Full

Cycles5

Conversion rate is the clock rate after the divider.

Refer to Figure 3 for timing diagram.

Wake-up time ADC is defined as the time required for the ADC to return to normal operation from power-down mode.

Wake-up time output is defined as the time required for JESD204B output to return to normal operation from power-down mode.

Cycles refers to ADC conversion rate cycles.

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