AD7992

–13–

REV. PrH

PRELIMINARYTECHNICAL DATA

Bit

Mnemonic

Comment

D 7

DONTCARE

D 6

Single/Dual

AD7992 a Dual channel part..

D5, D4 CH2,CH1

These two channel address bits select which analog input channel is to be converted. A 1 in any

of bits D5 or D4 selects a channel for conversion.

If more than one channel bit is set this

indicates that the alternating channel sequence is to be used. Table V shows how these two

channel address bits are decoded. If D5 is selected the part will operate in Dual channel mode,

with the Reference for the ADC being taken from the Supply voltage( D6 set to 0 for Dual

channel mode).

D 3

F L T R

The value written to this bit of the Control Register determines whether the filtering on SDA

and SCL is enabled or to be bypassed. If this bit is a 1 then the the filtering is enabled, if it is

a 0, then the filtering is bypassed.

D 2

ALERT EN

The hardware ALERT function is enabled if this bit is set to 1 and disabled if set to 0. This bit

is used in conjunction with the BUSY/ALERT bit to determine if the ALERT/BUSY pin will

act as an ALERT or a BUSY function. (See Table VI.)

D 1

BUSY/ALERT

This bit is used in conjunction with the ALERT EN bit to determine if

the ALERT/BUSY

output, pin 8, will act as an ALERT or BUSY function (see TABLE V1), or if pin 8 is

configured as an ALERT output pin, if it is to be reset. When reading the Configuration

registerD1 will always be a 0 when D2 is a 1.

D 0

BUSY/ALERT

This bit determines the active polarity of the ALERT/BUSY pin regardless of whether it is

POLARITY

configured as an ALERT or BUSY output. It is active low if this bit is set to 0, and it is active

high if set to 1.

Table VI. ALERT/BUSY Function

D2

D1

ALERT/BUSY Pin Configuration

0

0

Pin does not provide any interrupt signal.

0

1

Pin configured as a BUSY output.

1

0

Pin configured as an ALERT output.

1

1

Resets ALERT output pin, Alert_Flag bit in

Conversion Result Reg, and entire Alert

Status Reg ( if any active).

CONVERSION RESULT REGISTER

The Conversion Result Register is a 16-bit read-only reg-

ister which stores the conversion reading from the ADC in

Straight Binary format. A two Byte read operation is nec-

essary to read data from this register. Table VIIa shows

the contents of the first byte to be read while Table VIIb

show the contents of the second byte to be read from

AD7992.

Table VIIa.

Conversion Value Register (First Read)

D15

D14

D13

D12

D11

D10

D9

D8

Alert_Flag Zero

Zero CH I.D. M S B B10

B 9

B 8

Table VIIb.

Conversion Value Register (Second Read)

D7

D6

D5

D4

D3

D2

D1

D0

B7

B6

B5

B4

B3

B2

B1

B0

The AD7992 conversion result consists of an Alert_Flag

bit, two leading zeros, a Channel Identifier bit and the 12

bit data result.

The Alert_Flag bit indicates whether the conversion result

being read has violated a limit register associated with the

channel. This is followed by two leading zeros and a

Channel Indentifier bit indicating which channel the con-

version result corresponds to. The 12-bit conversion result

then follows MSB first.

Table V. Channel Selection

D5

D4

Analog Input Channel

CH2 CH1

0

0

No Conversion

0

1

1

0

1

1

Sequence between Channel 1 and Channel 2,

beginning with Ch1

LIMIT REGISTERS

The AD7992 has two pairs of limit registers, each to store

high and low conversion limits for both analog input

channels. Each pair of limit registers has an associated

hysteresis register. All six registers are 16-bits wide, of

which only the 12 LSBs of each are used. On power-up,

isters will be zeroscale by default.