ADAV803ASTZ datasheet(38/61 Pages) AD

38 / 61 page

ADAV803

Rev. A | Page 37 of 60

Receiver Buffer Configuration—Address 0001011 (0x0B)

Table 35. Receiver Buffer Configuration Register Bit Map

Reserved

RxBCONF5

RxBCONF4

RxBCONF3

RxBCONF2

RxBCONF1

RxBCONF0

Table 36. Receiver Buffer Configuration Register Bit Descriptions

Bit Name

Description

RxBCONF5

If the user bits are formatted according to the IEC60958-3 standard and the DAT category is detected, the user bit

interrupt is enabled only when there is a change in the start (ID) bit.

0 = User bit interrupt is enabled in normal mode.

1 = If the DAT category is detected, the user bit interrupt is enabled only if there is a change in the start (ID) bit.

RxBCONF4

This bit determines whether Channel A and Channel B user bits are stored in the buffer together or separated

between A and B.

0 = User bits are stored together.

1 = User bits are stored separately.

RxBCONF3

Defines the function of RxCSBINT.

0 = RxCSBINT are set when a new block of receiver channel status is read, which is 192 audio frames.

1 = RxCSBINT is set only if the first five bytes of the receiver channel status block changes from the previous

channel status block.

RxBCONF[2:1]

Defines the user bit buffer.

00 = User bits are ignored.

01 = Updates the second user bit buffer when the first user bit buffer is full.

10 = Formats the received user bits according to Byte 1, Bit 4 to Bit 7, of the channel status, if the PRO bit is set. If

the PRO bit is not set, formats the user bits according to the IEC60958-3 standard.

11 = Reserved.

RxBCONF0

Defines the user bit buffer size, if RxBCONF[2:1] = 01.

0 = 384 bits with Preamble Z as the start of the buffer.

1 = 768 bits with Preamble Z as the start of the buffer.

Transmitter Control—Address 0001100 (0x0C)

Table 37. Transmitter Control Register Bit Map

Reserved

TxVALIDITY

TxRATIO2

TxRATIO1

TxRATIO0

TxCLKSEL1

TxCLKSEL0

TxENABLE

Table 38. Transmitter Control Register Bit Descriptions

Bit Name

Description

TxVALIDITY

This bit is used to set or clear the VALIDITY bit in the AES3/S/PDIF transmit stream.

0 = Audio is suitable for digital-to-analog conversion.

1 = Audio is not suitable for digital-to-analog conversion.

TxRATIO[2:0]

Determines the AES3/S/PDIF transmitter to AES3/S/PDIF receiver ratio.

000 = Transmitter to receiver ratio is 1:1.

001 = Transmitter to receiver ratio is 1:2.

010 = Transmitter to receiver ratio is 1:4.

101 = Transmitter to receiver ratio is 2:1.

110 = Transmitter to receiver ratio is 4:1.

TxCLKSEL[1:0]

Selects the clock source for the AES3/S/PDIF transmitter.

00 = Internal Clock 1 is the clock source for the transmitter.

01 = Internal Clock 2 is the clock source for the transmitter.

10 = Recovered PLL clock is the clock source for the transmitter.

11 = Reserved.

TxENABLE

Enables the AES3/S/PDIF transmitter.

0 = AES3/S/PDIF transmitter is disabled.

1 = AES3/S/PDIF transmitter is enabled.

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