AD6679 datasheet(63/82 Pages) AD

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AD6679

Data Sheet

Rev. B | Page 62 of 81

DIGITAL OUTPUTS

The AD6679 output drivers are for standard ANSI LVDS, but

optionally the drive current can be reduced using Register 0x56A.

The reduced drive current for the LVDS outputs potentially

reduces the digitally induced noise.

As detailed in the AN-877 Application Note, Interfacing to High

Speed ADCs via SPI, the data format can be selected for offset

binary, twos complement, or gray code when using the SPI control.

The AD6679 has a flexible three-state ability for the digital output

pins. The three-state mode is enabled when the device is set for

power-down mode.

TIMING

The AD6679 provides latched data with a pipeline delay of

33 input sample clock cycles. Data outputs are available one

propagation delay (tPD) after the rising edge of the clock signal.

Minimize the length of the output data lines and the corresponding

loads to reduce transients within the AD6679. These transients

can degrade converter dynamic performance.

The minimum conversion rate of the AD6679 is 300 MSPS. At

clock rates below 300 MSPS, dynamic performance may degrade.

DATA CLOCK OUTPUT

The AD6679 also provides a data clock output (DCO) intended

for capturing the data in an external register. Figure 4 through

Figure 11 show the timing diagrams of the AD6679 output

modes. The DCO relative to the data output can be adjusted using

per step ranging from 0° to 270°. Data is output in a DDR format

and is aligned to the rising and falling edges of the clock derived

from the DCO.

ADC OVERRANGE

The ADC overrange (OR) indicator is asserted when an overrange

is detected on the input of the ADC. The overrange condition is

determined at the output of the ADC pipeline and, therefore, is

subject to a latency of 33 ADC clocks. An overrange at the input is

indicated by the OR bit, 33 clock cycles after it occurs.

Table 35. LVDS Output Configurations1

Parallel Output Mode

No. of Virtual

Converters

Supported

Maximum

Virtual

Converter

Resolution

(Bits)

Output

Line

Rate2, 3

VDR

Supported

NSR

Decimation

Rates

Supported

DDC Decimation

Rates Supported

Outputs Required

Real

Output

Complex

Output

Parallel Interleaved,

One Virtual Converter

(Register 0x568 = 0x0)

1 × fOUT

Yes

1, 2

1, 2, 4, 8

N/A

DCO±, OVR±, and

D0± to D13±

Parallel Interleaved,

Two Virtual Converters

(Register 0x568 = 0x1)

2 × fOUT

Yes

1, 2

1, 2, 4, 8

2, 4, 8, 16

DCO±, OVR±, and

D0± to D13±

Channel Multiplexed,

One Virtual Converter

(Register 0x568 = 0x2)

2 × fOUT

Yes

1, 2

1, 2, 4, 8

N/A

DCO±, OVR±,

A Dx/Dy±

Channel Multiplexed,

Two Virtual Converters

(Register 0x568 = 0x3)

2 × fOUT

Yes

1, 2

1, 2, 4, 8

2, 4, 8, 16

DCO±, OVR±, A Dx/

Dy±, and B Dx/Dy±

Byte Mode, One Virtual

Converter

(Register 0x568 = 0x4)

2 × fOUT

1, 2

1, 2, 4, 8

N/A

DCO±, STATUS±, and

DATA0± to DATA7±

Byte Mode, Two Virtual

Converters

(Register 0x568 = 0x5)

4 × fOUT

2, 4, 8

2, 4, 8, 16

DCO±, STATUS±, and

DATA0± to DATA7±

Byte Mode, Four Virtual

Converters

(Register 0x568 = 0x6)

8 × fOUT

N/A

24, 4, 8

24, 4, 8, 16

DCO±, STATUS±, and

DATA0± to DATA7±

Byte Mode, Eight Virtual

Converters

(Register 0x568 = 0x7)

16 × fOUT

N/A

44, 8, 16

DCO±, STATUS±, and

DATA0± to DATA7±

N/A means not applicable.

fOUT = ADC Sample Rate ÷ chip decimation ratio, where fOUT is the output sample rate.

Maximum output line rate is 1000 Mbps.

fOUT ≤ 125 MSPS.

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