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AD6679

Data Sheet

Rev. B | Page 20 of 81

Pin No.

Mnemonic

Type

Description

H10

V_1P0

Input/DNC

1.0 V Reference Voltage Input/Do Not Connect. This pin

is configurable through the SPI as a no connect or as an

input. Do not connect this pin if using the internal

reference. This pin requires a 1.0 V reference voltage

input if using an external voltage reference source.

A7, A8

CLK+, CLK−

Input

Clock Input True/Complement.

CMOS Outputs

J14, J1

FD_A, FD_B

Output

Fast Detect Outputs for Channel A and Channel B.

Digital Inputs

C7, C8

SYNC+,

SYNC−

Input

Active High LVDS Sync Input—True/Complement.

Data Outputs

N6, P6

D0−, D0+

Output

LVDS Lane 0 Output Data—Complement/True.

M2, M1

D1−, D1+

Output

LVDS Lane 1 Output Data—Complement/True.

N1, P1

D2−, D2+

Output

LVDS Lane 2 Output Data—Complement/True.

N2, P2

D3−, D3+

Output

LVDS Lane 3 Output Data—Complement/True.

N3, P3

D4−, D4+

Output

LVDS Lane 4 Output Data—Complement/True.

N4, P4

D5−, D5+

Output

LVDS Lane 5 Output Data—Complement/True.

N5, P5

D6−, D6+

Output

LVDS Lane 6 Output Data—Complement/True.

N9, P9

D7−, D7+

Output

LVDS Lane 7 Output Data—Complement/True.

N10, P10

D8−, D8+

Output

LVDS Lane 8 Output Data—Complement/True.

N11, P11

D9−, D9+

Output

LVDS Lane 9 Output Data—Complement/True.

N12, P12

D10−, D10+

Output

LVDS Lane 10 Output Data—Complement/True.

N13, P13

D11−, D11+

Output

LVDS Lane 11 Output Data—Complement/True.

N14, P14

D12−, D12+

Output

LVDS Lane 12 Output Data—Complement/True.

M13, M14

D13−, D13+

Output

LVDS Lane 13 Output Data—Complement/True.

L13, L14

OVR−, OVR+

Output

LVDS Overrange Output Data—Complement/True.

K13, K14

DCO−, DCO+

Output

LVDS Digital Clock Output Data—Complement/True.

Device Under Test (DUT) Controls

SDIO

Input/output

SPI Serial Data Input/Output.

SCLK

Input

SPI Serial Clock.

CSB

Input

SPI Chip Select (Active Low).

J13

PDWN/STBY

Input

Power-Down Input (Active High)/Standby. The

operation of this pin depends on the SPI mode and can

be configured in power-down or standby mode.

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