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AD9856/PCB Arkusz danych(PDF) 19 Page - Analog Devices |
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AD9856/PCB Arkusz danych(HTML) 19 Page - Analog Devices |
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19 / 37 page ![]() AD9856 Rev. C | Page 18 of 36 TxENABLE D(11:0) INTERNAL I INTERNAL Q I0 Q0 I1 Q1 I2 Q2 I3 Q3 I4 Q4 I0 I1 I2 I3 Q0 Q2 Q3 Q1 Figure 24. 12-Bit Input Mode, Classic Burst Timing TxENABLE D(11:0) INTERNAL I INTERNAL Q I0 Q0 I1 Q1 I2 Q2 I3 Q3 I4 Q4 I0 I1 I2 I3 Q0 Q1 Q2 Q3 Figure 25. 12-Bit Input Mode, Alternate TxENABLE Timing TxENABLE D(11:6) INTERNAL I INTERNAL Q I0 I1 Q0 Q1 I0(11:6) I0(5:0) Q0(5:0) I1(11:6) I1(5:0) Q1(11:6) Q1(5:0) I2(11:6) Q0(11:6) I2(5:0) Figure 26. 6-Bit Input Mode, Burst Mode Timing I0(11:9) I0(8:6) I0(5:3) I0(2:0) Q0(11:9) Q0(8:6) Q0(5:3) Q0(2:0) I1(11:9) I1(8:6) TxENABLE D(11:9) INTERNAL I INTERNAL Q I0 Q0 Figure 27. 3-Bit Input Mode, Burst Mode Timing TxENABLE D(11:0) INTERNAL I INTERNAL Q IN QN I0 Q0 I1 Q1 IN IN–2 IN–1 QN–2 QN–1 QN LOGIC 0 LOGIC 0 I0 Q0 Figure 28. End of Burst Mode Input Timing |
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