AD9856SLASHPCB datasheet(20/37 Pages) AD

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AD9856

Rev. C | Page 19 of 36

Continuous Mode Input Timing

The AD9856 is configured for continuous mode input timing

by writing the continuous mode bit true (Logic 1). The

continuous mode bit is in register address 01h, Bit 6. The

AD9856 must be configured for full-word input format when

operating in continuous mode input timing. The input data rate

equations described previously for full-word mode apply for

continuous mode. Figure 25, which is the alternate burst mode

timing diagram, is also the continuous mode input timing.

Figure 29 and Figure 30 show what the internal data assembler

presents to the signal processing logic when the TxENABLE

input is held static for greater than one input sample period.

Please note that the timing diagram shown in Figure 29 and

Figure 30 detail INCORRECT timing relationships between

TxENABLE and data. They are only presented to indicate that

the AD9856 resynchronizes properly after detecting a rising

edge of TxENABLE. Also note that the significant difference

between burst and continuous mode operation is that in

addition to synchronizing the data, TxENABLE is used to

indicate whether an I or Q input is being sampled.

Do not engage continuous mode simultaneously with the

REFCLK multiplier function. This corrupts the CIC inter-

polating filter, forcing unrecoverable mathematical overflow

that can only be resolved by issuing a RESET command. The

problem is due to the PLL failing to be locked to the reference

clock while nonzero data is being clocked into the interpolation

stages from the data inputs. The recommended sequence is to

first engage the REFCLK multiplier function (allowing at least

1 ms for loop stabilization) and then engage continuous mode

via software.

IN+1

QN+1

IN+2

QN+2

IN+3

QN+3

IN+4

QN+4

IN+5

IN+1

IN–1

IN+2

IN+3

TxENABLE

D(11:0)

INTERNAL I

INTERNAL Q

QN–1

QN+3

QN+4

IN+4

Figure 29. Continuous Mode Input Timing—TxENABLE Static High (for illustrative purposes only)

IN+1

QN+1

IN+2

QN+2

IN+3

QN+3

IN+4

QN+4

QN+2

QN+1

IN–1

IN+3

TxENABLE

D(11:0)

INTERNAL I

INTERNAL Q

QN–1

QN+3

Figure 30. Continuous Mode Input Timing—TxENABLE Static Low (for illustrative purposes only)

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