CS42418 datasheet(24/67 Pages) CIRRUS

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CS42418

3.5.4.3

OLM Config #3

This configuration will support up to 8 channels of DAC data, and 6 channels of ADC data. OLM Config

#3 will handle up to 20-bit ADC samples at an Fs of 48 kHz and 24-bit DAC samples at an Fs of 48 kHz.

Since the ADCs data stream is configured to use the ADC_SDOUT output and the internal and external

ADCs are clocked from the ADC_SP, then the sample rate for the DAC Serial Port can be different from

the sample rate of the ADC serial port.

Description

Functional Mode Register (addr = 03h)

Set DAC_FMx = 00,01,10

DAC_LRCK can run at SSM, DSM, or QSM independent of ADC_LRCK

Set ADC_FMx = 00,01,10

ADC_LRCK can run at SSM, DSM, or QSM independent of DAC_LRCK

Set ADC_CLK_SEL = 1

Configure ADC_SDOUT to be clocked from the ADC_SP clocks.

Interface Format Register (addr = 04h)

Set DIFx bits to proper serial format

Select the digital interface format when not in one line mode

Set ADC_OLx bits = 00,01

Select ADC operating mode, see table below for valid combinations

Set DAC_OLx bits = 00,01,10

Select DAC operating mode, see table below for valid combinations

Misc. Control Register (addr = 05h)

Set DAC_SP M/S = 1

Set DAC Serial Port to master mode.

Set ADC_SP M/S = 0 or 1

Set ADC Serial Port to master mode or slave mode.

Set EXT ADC SCLK = 0

Identify external ADC clock source as ADC Serial Port.

DAC Mode

Not One Line Mode

One Line Mode #1

One Line Mode #2

ADC Mode

Not One

Line Mode

DAC_SCLK=64Fs

DAC_LRCK=SSM/DSM/QSM

ADC_SCLK=64Fs

ADC_LRCK=SSM/DSM/QSM

DAC_SCLK=128Fs

DAC_LRCK=SSM/DSM

ADC_SCLK=64Fs

ADC_LRCK=SSM/DSM/QSM

DAC_SCLK=256Fs

DAC_LRCK=SSM

ADC_SCLK=64Fs

ADC_LRCK=SSM/DSM/QSM

One Line

Mode #1

DAC_SCLK=64Fs

DAC_LRCK=SSM/DSM/QSM

ADC_SCLK=128Fs

ADC_LRCK=SSM

DAC_SCLK=128Fs

DAC_LRCK=SSM/DSM

ADC_SCLK=128Fs

ADC_LRCK=SSM

DAC_SCLK=256Fs

DAC_LRCK=SSM

ADC_SCLK=128Fs

ADC_LRCK=SSM

One Line

Mode #2

not valid

SC LK_ POR T1

LRC K_PO RT1

SDIN _PO RT1

SC LK_ POR T2

LRC K_PO RT2

SDO UT1_P ORT2

SDO UT2_P ORT2

SDO UT3_P ORT2

SDO UT4_P ORT2

RM CK

AD CIN1

AD CIN2

MC LK

SDO UT1

SDO UT2

LR CK

SCL K

64Fs,128Fs

DIG ITAL AUD IO

PRO CESSO R

CS5361

ADC_ SCL K

AD C_L RCK

ADC_ SDO UT

DAC _SCL K

D AC_L RCK

DAC_ SDIN1

DAC_ SDIN2

DAC_ SDIN3

DAC_ SDIN4

MCLK

64Fs,128Fs,256Fs

Figure 15. OLM Configuration #3

CS42418

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