MCP18480 datasheet(37/64 Pages) MICROCHIP

37 / 64 page

 2003 Microchip Technology Inc.

DS20091B-page 37

MCP18480

OVO

Overvoltage detect.

Typically for normal operation. This pin is tied to VNEG.

This feature allows the overvoltage detection input to monitor an over-

voltage condition across the power module. The voltage is sensed at

the drain of the external MOSFET. The voltage across the load is inter-

nally determined based upon:

• The voltage difference between system ground and the voltage

on the VNEG pin

• The voltage difference between the drain of the external FET and

the voltage on the VNEG pin

An external resistor divider network (ROVO1 and ROVO2) is attached

between the drain of the external MOSFET and the VNEG pin (ROVO1

is connected between the drain of the external MOSFET and the OVO

pin, while ROVO2 is connected between the OVO pin and the VNEG

pin).

When the voltage across the external MOSFET (source-to-drain)

equals system ground voltage (- VNEG +), the maximum desired load

voltage, the GATE pin is forced to the voltage on the VNEG pin

(disabling the external MOSFET).

To detect Overvoltage on the board (instead of the load) directly,

connect the OVO pin to the VNEG pin.

PWRGOOD

Power Good indicator.

This state of the output is determined by four conditions. These are:

• Undervoltage

• Overvoltage

• Current Limit

• External FET is fully-enhanced (from DRAINTH pin on power-up)

PWRGOOD is a CMOS logic voltage (VNEG or VNEG+12V).

PWRGOOD is active when the device has completed power-up and

the system is neither in an Undervoltage or Overvoltage condition.

Connecting the RISET pin to the VNEG pin configures the PWRGOOD

pin to be active high. Connecting the RISET pin to the VREF pin config-

ures the PWRGOOD pin to be active low.

ENABLE

TTL

Enable Gate driver.

Used to enable the GATE pin and assert the PWRGOOD pin. The

ENABLE pin is active-high and is internally pulled up to 5V. This pin is

pulled low by the user to clear the current limit latch when a current-

limit fault occurs with RESTART high, or to disable the GATE pin.

H = Enable the GATE and PWRGOOD pins.

L = Disables the GATE pin, deasserts the PWRGOOD pin and clears

current limit latch.

When the ENABLE pin is high, fault conditions will disable the GATE

pin and deasserts the PWRGOOD pin.

TABLE 3-1:

MCP18480 PIN DESCRIPTIONS (CONTINUED)

Pin Name

Number

Direction

Buffer

Type

Description

SSOP

Legend: TTL = TTL compatible input

ST = Schmitt Trigger input with CMOS levels

I = Input

O = Output

P = Power

CMOS = CMOS-compatible input

A = Analog

D = Digital

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