MCP18480 datasheet(46/64 Pages) MICROCHIP

46 / 64 page

MCP18480

DS20091B-page 46

 2003 Microchip Technology Inc.

6.8.4

CURRENT LIMIT BLOCK

An excessive current flowing through the external FET

is sensed as a voltage across an external resistor

connected between the FET’s source and VNEG.

The drain voltage is sensed with a resistor divider net-

work, as shown in Figure 4-1 and Figure 4-2. The volt-

age tap is applied to a circuit whose output is 50 mV

above VNEG when the drain of the external FET is at

VNEG. The output is 12 mV when the VFB pin is

≥ VNEG +0.5V. This output voltage is the Current Limit

Feedback (CLFB) signal to the gate driver block for use

in the fold-back current-limiting.

The CLFB voltage serves as the reference for a com-

parator whose other input monitors the voltage across

the current limit sense resistor in series with the source

of the external FET. When the SENSE pin exceeds the

voltage on CLFB, a comparator output goes high to

start the timer (see Section 6.8.5). The VDS dependent

threshold for the current limit helps keep the FET within

its safe operating area.

Another comparator in the current-limiting block

watches the SENSE pin for potentially catastrophic

over-current conditions, which require immediate ter-

mination of conduction in the pass MOSFET. The out-

put of this comparator trips a comparator used in the

TIMER block to skip the first part of the timeout cycle

and go straight to the “off” period. In some cases, the

user may want to program the system to shut off imme-

diately if there is a short-circuit condition that exceeds

a desired level. To use this feature, connect a divider

between the VREFIN pin and the VNEG pin, with its cen-

tertap at the CL input pin. The circuit breaker current

that would trigger this mode is given by Equation 6-5.

EQUATION 6-5:

CIRCUIT BREAKER

THRESHOLD

If this function is not needed in a particular application,

it can be disabled by connecting the CL pin to the

VREFIN pin. Equation 6-6 shows the current of the CL

pin during current-limiting.

EQUATION 6-6:

CL PIN CURRENT

6.8.5

TIMER BLOCK

Since the external FET can survive brief over-current

episodes, it is unnecessary to turn off the FET instantly

when the current rises too high (see external FET data

sheet). The timer circuit uses the output of the compar-

ator in the current-limiting block to begin charging an

external capacitor with 16 • IRISET (typically 160 µA)

when an over-current condition is detected. When the

voltage on the capacitor ramps up to 1.25V, a compar-

ator output goes high. This output goes to another

block that tells the gate driver to turn the external FET

off and deassert the PWRGOOD pin. The complemen-

tary output of the timer changes the state of a hystere-

sis circuit that drops the reference input of the

comparator to VNEG + 100 mV (± 10 mV).

When the FET is off, the current through it drops to

zero, so that the voltage across the current sense resis-

tor also goes to zero and the current limit signal to the

timer block goes away. The timer capacitor starts to

discharge at a rate set by the external resistor, RDISCH.

Equation 6-7 shows the equations used to calculate the

current at the TIMER pin. This current is used for other

calculations.

EQUATION 6-7:

TIMER PIN CURRENT

CALCULATIONS

The delay between the inception of the over-current

condition and the deactivation of the FET is given by

Equation 6-8.

EQUATION 6-8:

OVER-CURRENT FAULT

DELAY

The time required to reset the timer and reactivate the

gate driver is given by Equation 6-9.

EQUATION 6-9:

OVER-CURRENT

REACTIVATION DELAY

As described above, the timer circuit operates as a

free-running, multi-vibrator, if RESTART is low.

ICAT

VREFIN

RCL1 RCL2

-------------------------------



 R

CL2

•

RSENSE

-------------------------------------------------------

> 0.5V

50 mV

12 mV

SENSE

for V

FB > 0.5V, VSENSE = 0.012V

ICL

VSENSE

RSENSE

------------------

VSENSE

0.76

0.05V

VDS RFB2

RFB1 RFB2

-------------------------------

–



 0.012V

Legend: I

RISET is the current through the external

ISET resistor

ITIMER

16 IRISET

•

Typical

ITIMER

10 IRISET

•

Minimum

ITIMER

20 IRISET

•

Maximum

TCLD1

CTIMER

ITIMER

------------------- 1.25

•

TCLD2

9.2 CTIMER

•

RDISCH

•

MCP18480 Arkusz danych(PDF) 46 Page - Microchip Technology

MCP18480 Arkusz danych(HTML) 46 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Arkusz danych Pobierz

Link URL