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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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XRT83SL34 Arkusz danych(PDF) 37 Page - Exar Corporation |
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XRT83SL34 Arkusz danych(HTML) 37 Page - Exar Corporation |
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37 / 80 page  XRT83SL34 QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PRELIMINARY REV. P1.0.8 34 RECEIVE For N+1 redundancy, the receivers on the primary cards should be programmed for internal impedance mode. The receivers on the backup card should be programmed for external impedance mode. Since there is no external resistor in the circuit, the receivers on the backup card will be high impedance. Select the impedance for the desired mode of operation, T1/E1/J1. To swap the primary card, set the backup card to internal impedance mode, then the primary card to external impedance mode. See Figure 17. for a simplified block diagram of the receive section for a N+1 redundancy scheme. NOTE: For simplification, the over voltage protection circuitry was omitted. FIGURE 17. SIMPLIFIED BLOCK DIAGRAM - RECEIVE SECTION FOR N+1 REDUNDANCY B a ckp lane In te rface P rim ary C a rd X R T 83S L3 4 Rx Line In te rface C a rd P rim ary C a rd X R T 83S L3 4 Rx P rim ary C a rd X R T 83S L3 4 Rx B a ckup C a rd X R T 83S L3 4 Rx R xT S E L =1 , In te rn a l R xT S E L =1 , In te rn a l R xT S E L =1 , In te rn a l R xT SEL=1 , Exte rnal T 1 /E 1 Line T 1 /E 1 Line T 1 /E 1 Line 1:1 1:1 1:1 |
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