XRT83SL34 datasheet(50/80 Pages) EXAR

50 / 80 page

XRT83SL34

QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.0.8

PRELIMINARY

JASEL1_n

Jitter Attenuator select bit 1: The JASEL1 and JASEL0 bits

are used to disable or place the jitter attenuator of each chan-

nel independently in the transmit or receive path.

R/W

JASEL0_n

Jitter Attenuator select bit 0: See description of bit D3 for the

function of this bit.

R/W

JABW_n

Jitter Attenuator Bandwidth Select: In E1 mode, set this bit

to “1” to select a 1.5Hz Bandwidth for the Jitter Attenuator. The

FIFO length will be automatically set to 64 bits. Set this bit to

“0” to select 10Hz Bandwidth for the Jitter Attenuator in E1

mode. In T1 mode the Jitter Attenuator Bandwidth is perma-

nently set to 3Hz, and the state of this bit has no effect on the

Bandwidth.

R/W

FIFOS_n

FIFO Size Select: See table of bit D1 above for the function of

this bit.

R/W

TABLE 20: MICROPROCESSOR REGISTER #1, BIT DESCRIPTION

JASEL1

bit D3

JASEL0

bit D2

JA Path

JA Disabled

JA in Transmit Path

JA in Receive Path

FIFOS_n

bit D0

JABW

bit D1

Mode

FIFO

Size

1.5

JA B-W

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