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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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T1024 Arkusz danych(PDF) 32 Page - Freescale Semiconductor, Inc |
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T1024 Arkusz danych(HTML) 32 Page - Freescale Semiconductor, Inc |
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32 / 49 page  POR & Override switch T1024 CPLD CPLD Register cfg_xxx Figure 2-21. DIP switch definition The table below shows how POR configuration is done through switches. Table 2-11. POR configuration through switches Switch Signal name Pin name Signal meaning Setting SW1[1:8] cfg_rcw_src[0:7] IFC_AD[8:15] Reset configuration word source For details, see T1024 QorIQ Integrated Multicore Communications Processor Data Sheet. SW2[1] cfg_rcw_src[8] IFC_CLE Reset configuration word source For details, see T1024 QorIQ Integrated Multicore Communications Processor Data Sheet. SW2[2] cfg_ifc_te IFC_TE IFC external transceiver enable polarity select 0: IFC drives logic 1 for TE assertion 1: IFC drives logic 0 for TE assertion SW2[3] cfg_pll_config_sel _b IFC_A18 Reserved Reserved SW2[4] cfg_por_ainit IFC_A19 Reserved Reserved SW2[5:6] cfg_svr[0:1] IFC_A[16:17] Reserved Reserved SW2[7] cfg_dram_type IFC_A21 DRAM type selection Reserved SW2[8] cfg_rsp_dis IFC_AVD Reserved Reserved SW3[1] cfg_eng_use0 IFC_WE0 Sys_clock selection Reserved SW3[2] cfg_eng_use1 IFC_OE_N ON (0): Choose 10G working mode OFF (1): Choose 2.5G working mode SW3[3] cfg_eng_use2 IFC_WP_N Reserved SW3[4] BOOT_FLASH_S EL - Boot flash selection 0: NOR flash connects to CS0, NAND flash connects to CS1 1:NOR flash connects to CS1, NAND flash connects to CS0 SW3[5:7] CFG_VBANK[0:2] - NOR flash bank select 000: boot from VBANK0 with RCW 0x095 for 10G XFI mode Table continues on the next page... DIP switch definition QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/2015 32 Freescale Semiconductor, Inc. |
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