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AM50DL128CH Arkusz danych(PDF) 55 Page - Advanced Micro Devices

Numer części AM50DL128CH
Szczegółowy opis  STACKED MULTI-CHIP PACKAGE (MCP) FLASH MEMORY AND SRAM
PDF  64 Pages
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Producent  AMD [Advanced Micro Devices]
Strona internetowa  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM50DL128CH Arkusz danych(HTML) 55 Page - Advanced Micro Devices

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October 6, 2003
Am50DL128CH
53
ADV ANCE
I N FO RMAT I O N
pSRAM AC CHARACTERISTICS
Read Cycle
Notes:
1. t
OD, tODo, tBD, and tODW are defined as the time at which
the outputs achieve the open circuit condition and are
not referenced to output voltage levels.
2. If CE#, LB#, or UB# goes low at the same time or before
WE# goes high, the outputs will remain at high impedance.
3. If CE#, LB#, or UB# goes low at the same time or after WE#
goes low, the outputs will remain at high impedance.
Figure 27.
Pseudo SRAM Read Cycle
Parameter
Symbol
Description
Speed
Unit
56, 70
85
t
RC
Read Cycle Time
Min
70
85
ns
t
ACC
Address Access Time
Max
70
85
ns
t
CO
Chip Enable Access Time
Max
70
85
ns
t
OE
Output Enable Access Time
Max
25
ns
t
BA
Data Byte Control Access Time
Max
25
ns
t
COE
Chip Enable Low to Output Active
Min
10
ns
t
OEE
Output Enable Low to Output Active
Min
0
ns
t
BE
Data Byte Control Low to Output Active
Min
0
ns
t
OD
Chip Enable High to Output High-Z
Max
20
ns
t
ODO
Output Enable High to Output High-Z
Max
20
ns
t
BD
Data Byte Control High to Output High-Z
Max
20
ns
t
OH
Output Data Hold from Address Change
Min
10
ns
t
PM
Page Mode Time
Min
70
ns
t
PC
Page Mode Cycle Time
Min
30
ns
t
AA
Page Mode Address Access Time
Max
30
ns
t
AOH
Page Output Data Hold Time
Min
10
ns
tRC
tACC
Addresses
A20 to A0
CE#1
CE2
OE#
WE#
LB#, UB#
DOUT
DQ15 to DQ0
tCO
tOH
Fixed High
High-Z
High-Z
tOE
tBA
tOD
tODO
tBD
Valid Data Out
Indeterminate
tBE
tOEE
tCOE



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