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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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AM50DL128CH Arkusz danych(PDF) 57 Page - Advanced Micro Devices |
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AM50DL128CH Arkusz danych(HTML) 57 Page - Advanced Micro Devices |
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57 / 64 page  October 6, 2003 Am50DL128CH 55 ADV ANCE I N FO RMAT I O N pSRAM AC CHARACTERISTICS Write Cycle Notes: 1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied. 2. If OE# is high during the write cycle, the outputs will remain at high impedance. 3. If CE#1ps, LB# or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance. 4. If CE#1ps, LB# or UB# goes high at the same time or before WE# goes high, the outputs will remain at high impedance. Figure 29. Pseudo SRAM Write Cycle—WE# Control Parameter Symbol Description Speed Unit 56, 70 85 t WC Write Cycle Time Min 70 85 ns t WP Write Pulse Time Min 50 60 ns t CW Chip Enable to End of Write Min 60 70 ns t BW Data Byte Control to End of Write Min 60 70 ns t AW Address Valid to End of Write Min 60 70 ns t AS Address Setup Time Min 0 ns t WR Write Recovery Time Min 0 ns t ODW WE# Low to Write to Output High-Z Max 20 ns t OEW WE# High to Write to Output Active Min 0 ns t DS Data Set-up Time Min 30 t DH Data Hold from Write Time Min 0 ns t CH CE2 Hold Time Min 300 µs t CEH Chip Enable High Pulse Width Min 10 ns t WEH Write Enable High Pulse Width Min 6 ns tWC tWP tAW tWEH tWR tCW tBW Valid Data In tAS tCH tOEW Addresses A20 to A0 WE# CE#1s CE2s LB#, UB# DIN DQ15 to DQ0 DOUT DQ15 to DQO tODW tDS tDH High-Z (Note 1) (Note 3) (Note 4) |
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