ADRF5740

Data Sheet

Rev. 0 | Page 10 of 13

THEORY OF OPERATION

The ADRF5740 incorporates a 4-bit fixed attenuator array that

offers an attenuation range of 22 dB in 2 dB steps. An integrated

driver provides parallel mode control of the attenuator array.

The ADRF5740 has four digital control inputs, D2 (LSB) to D5,

to select the desired attenuation state in parallel mode, as shown

in Figure 23. Internally, there are two 8 dB stages, and these can be

controlled by the D4 and D5 pins.

POWER SUPPLY

The ADRF5740 requires a positive supply voltage applied to the

VDD pin and a negative supply voltage applied to the VSS pin.

Bypassing capacitors are recommended on the supply lines to

filter high frequency noise.

The power-up sequence is as follows:

1. Connect GND to ground.

2. Power up VDD and VSS. Power up VSS after VDD to

avoid current transients on VDD during ramp-up.

3. Power up the digital control inputs. The relative order of

the digital control inputs is not important. However,

powering the digital control inputs before the VDD supply

may inadvertently forward bias and damage the internal

ESD protection structures. To avoid this damage, use a

series 1 kΩ resistor to limit the current flowing into the

control pin.

4. Apply an RF input signal to ATTIN or ATTOUT.

The power-down sequence is the reverse order of the power-up

sequence.

Power-Up State

The ADRF5740 has internal pull-up resistors (see Figure 6).

The internal pull-up resistors set the attenuator to the

maximum attenuation state (22 dB) when the VDD and VSS

voltages are applied.

RF INPUT AND OUTPUT

Both RF ports (ATTIN and ATTOUT) are dc-coupled to 0 V.

DC blocking is not required at the RF ports when the RF line

potential is equal to 0 V.

The RF ports are internally matched to 50 Ω. Therefore,

external matching components are not required.

The ADRF5740 supports bidirectional operation at a lower

power level. The power handling of the ATTIN and ATTOUT

ports are different. Therefore, the bidirectional power handling is

defined by the ATTOUT port. Refer to the RF input power

specifications in Table 1.

Table 7. Recommended Truth Table

Attenuation State (dB)

D3

D2

Low

Low

Low

Low

0 (reference)

Low

Low

Low

High

2

Low

Low

High

Low

4

Low

Low

High

High

6

Low

High

Low

Low

8

Low

High

Low

High

10

Low

High

High

Low

12

Low

High

High

High

14

High

High

Low

Low

16

High

High

Low

High

18

High

High

High

Low

20

High

High

High

High

22

1

Any combination of the control voltage input states shown in Table 7

provides an attenuation equal to the sum of the bits selected.

2

D4 and D5 both correspond to the 8 dB state. D4 has slightly higher accuracy

over states at higher frequencies.

LATCH ENABLE

LE

D2

D3

D4

D5

RF

INPUT

RF

OUTPUT

2dB

4dB

8dB

8dB

Figure 23. Simplified Circuit Diagram