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LPS27HHTW Arkusz danych(PDF) 30 Page - STMicroelectronics |
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LPS27HHTW Arkusz danych(HTML) 30 Page - STMicroelectronics |
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30 / 55 page ![]() Figure 24. Only MIPI I3CSM active (INT_DRDY pin connected to Vdd_IO) I²C/I3C I3C bus case Dynamic Address Assignment Master resets DA I3C private R/W with and without 7Eh CCC commands Slave event management Error detection and recovery (1) INT1 pin connected to Vdd_IO Only I3C active 1. When the slave is MIPI I3CSM only, the I²C slave is always disabled. The address can be assigned using MIPI I3CSM SDR timing. LPS27HHTW I²C/MIPI I3CSM coexistence in LPS27HHTW DS13489 - Rev 1 page 30/55 |
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