LPS27HHTW datasheet(37/55 Pages) STMICROELECTRONICS

37 / 55 page

When the ODR bits are set to a value different than '000', the device is in Continuous mode and automatically

acquires a set of data (pressure and temperature) at the frequency selected through the ODR[2:0] bits.

Once the additional low-pass filter has been enabled through the EN_LPFP bit, it is possible to configure the

device bandwidth acting on the LPFP_CFG bit. See Table 19 for low-pass filter configurations.

Table 19. Low-pass filter configurations

EN_LPFP

LPFP_CFG

Additional low-pass filter status

Device bandwidth

Disabled

ODR/2

Enabled

ODR/9

Enabled

ODR/20

The BDU bit is used to inhibit the update of the output registers until both upper and lower (and XLOW) register

parts are read. In default mode (BDU = ‘0’) the output register values are updated continuously. If for any reason

it is not sure to read faster than the output data rate, it is recommended to set the BDU bit to ‘1’. In this way, the

content of the output registers is not updated until MSB, LSB and XLSB have been read which avoids reading

values related to different sample times.

9.7

CTRL_REG2 (11h)

Control register 2 (R/W)

BOOT

INT_H_L

PP_OD

IF_ADD_INC

SWRESET

LOW_NOISE_EN

ONE_SHOT

BOOT

Reboots memory content. Default value: 0

(0: normal mode; 1: reboot memory content)

INT_H_L

Interrupt active-high, active-low. Default value: 0

(0: active high; 1: active low)

PP_OD

Push-pull/open-drain selection on interrupt pad. Default value: 0

(0: push-pull; 1: open-drain)

IF_ADD_INC

Default value: 1

(0: disable; 1: enable)

SWRESET

Software reset. Default value: 0

(0: normal mode; 1: software reset).

The bit is self-cleared when the reset is completed.

LOW_NOISE_EN

Enables low noise (used only if ODR is lower than 100 Hz). Default value: 0

(0: low-current mode; 1: low-noise mode)

ONE_SHOT

Enables one-shot. Default value: 0

(0: idle mode; 1: a new dataset is acquired)

The BOOT bit is used to refresh the content of the internal registers stored in the Flash memory block. At device

power-up, the content of the Flash memory block is transferred to the internal registers related to the trimming

functions to allow correct behavior of the device itself. If for any reason the content of the trimming registers is

modified, it is sufficient to use this bit to restore the correct values. When the BOOT bit is set to '1', the content

of the internal Flash is copied into the corresponding internal registers and is used to calibrate the device. These

values are factory trimmed and they are different for every device. They allow the correct behavior of the device

and normally they should not be changed. At the end of the boot process, the BOOT bit is set again to '0' by

hardware. The BOOT bit takes effect immediately after it is set to 1.

LPS27HHTW

CTRL_REG2 (11h)

DS13489 - Rev 1

page 37/55

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