FUSB3307 datasheet(12/21 Pages) ONSEMI

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FUSB3307

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CC1 and CC2 Lines and USB−C Receptacle Assumptions

If a USB−C receptacle is used, CC1 and CC2 are

connected from the receptacle to the FUSB3307’s CC1 and

CC2 pins. If a hardwired connection (called “captive cable”

in Type−C and USB PD specifications) is desired, the CC

line is connected to CC1 (or CC2 if more convenient for

routing) and the VCONN line is connected to CC2 (or CC1)

pin not used above.

The design in the figures above assumes a Type C

receptacle (as opposed to captive cable) and all the following

descriptions are consistent with this configuration. Also

assumed is USB 2.0 only receptacle (D+ and D−) for a power

source application without data (that is, the USB D+ and D−

do not go to a USB PHY). All SuperSpeed lines (TX1+,

TX1−, RX1+, RX1−, TX2+, TX2−, RX2+, RX2−) are left

unconnected and the SBU1 (Side Band Use) and SBU2 pins

are not used.

Internally, the FUSB3307 pulls up CC1 and CC2

individually to VDD with currents that advertise 3 A

capability for this power source per USB Type C

specification. When a Sink device is connected to the

USB−C receptacle, the voltages on CC1 and CC2 will drop

down per Type C specification. The FUSB3307 will detect

a legitimate attach with the Sink and accordingly turn on the

VBUS FET Q1 (see VBUS Operation descriptions below).

If this design needs high−voltage, short−to−VBUS

protection on CC1 and CC2, the FUSB3307 protects the

CC1 and CC2 lines internally to the highest VBUS voltage

that is possible for USB PD. FUSB3307 also detects CC1

and CC2 pins in this over−voltage state and goes into the

Type C Disabled state. But it will take a finite amount of time

to detect an over−voltage event on CC1 or CC2, turn off the

load switch FET Q1 and discharge VBUS and thus the

over−voltage protection on CC1 and CC2 to protect these

I/Os. The CC1 and CC2 connector pins are physically close

to the VBUS connector pins which is why this need arises

more often than not as highlighted in Figure 9.

DISC

VDD

CC1

CC2

D+/PDIV1

D−/PDIV0

FUSB3307

USB Type−C

Detection

and Gate

Drivers

PD 3.0

Device Policy

Manager,

Policy

Engine,

Protocol &

PHY Layers

CV/CC

Regulation

ESD

7272

2 ESDM3551’s

ESD

7272

VBUS

Figure 9. CC1 and CC2 Proximity to VBUS Within

Type−C Connector

For USB PD traffic, per specification, the CC1 (and CC2)

line needs a capacitor to ground that is between 200 pF and

600 pF to minimize noise coupling from other signals within

the connector (especially if D+ and D− USB 2.0 data is sent

through the USB−C connector). Since the FUSB3307 has

very little internal capacitance on the CC1 and CC2 lines

(cReceiver in the electrical tables above), most of this has

to be supplied externally. The recommended value is 390 pF

capacitors from CC1 to ground and CC2 line to ground (C1

and C2 in Figure 5 and Figure 6) and the voltage rating is

dependent on the decision for high voltage protection above.

VBUS Operation

VBUS from the USB−C connector is typically connected

to a load switch NFET (Q1) source terminal whose gate

terminal is driven by the FUSB3307 gate driver via the

GATE pin. There isn’t a need for putting a resistor between

GATE pin and the gate of Q1 since when the load switch is

first turned on, upon attach of a Sink device via the USB−C

connector, the Sink device is not allowed to draw more than

500 mA. However, if desired for a soft turn−on of the FET,

a small (10 ohms typical) resistor can be placed between the

FUSB3307 GATE pin and the gate terminal of Q1. The drain

terminal of Q1 is connected to the power VCC which is at

5 V in the normal detached operation or in an initial USB−C

attach.

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