MCP48FVB28 datasheet(67/112 Pages) MICROCHIP

67 / 112 page

 2020 Microchip Technology Inc.

DS20006362A-page 67

MCP48FXBX4/8

The selection of the voltage is specified with the volatile

VRnB:VRnA Configuration bits (see Register 4-2).

There are nonvolatile and volatile VRnB:VRnA Config-

uration bits. On a POR/BOR event, the state of the

nonvolatile VRnB:VRnA Configuration bits is latched

into the volatile VRnB:VRnA Configuration bits.

When the user selects the VDD as reference, the VREF

pin voltage is not connected to the resistor ladder.

FIGURE 5-4:

Reference Voltage Selection

Implementation Block Diagram.

If the VREF pin is selected, then a selection has to be

made between the Buffered and Unbuffered mode.

5.2.1

BUFFERED MODE

The VREF pin voltage may be from 0.01V to VDD – 0.04V.

The input buffer (amplifier) provides low offset voltage,

low noise and a very high input impedance, with only

minor limitations on the input range and frequency

response.

5.2.2

UNBUFFERED MODE

The VREF pin voltage may be from VSS to VDD.

5.2.3

BAND GAP MODE

If the internal band gap is selected, then the external

VREF pin should not be driven and should only use

high-impedance loads.

The band gap output is buffered, but the internal

switches limit the current that the output should source

to the VREF pin. The resistor ladder buffer is used to

drive the band gap voltage for the cases of multiple

DAC outputs. This ensures that the resistor ladders are

always properly sourced when the band gap is

selected.

5.3

Internal Band Gap

The internal band gap is designed to drive the resistor

ladder buffer.

The resistance of a Resistor Ladder (RRL) is targeted to

be 140 k

 (40 k), which means a minimum

resistance of 100 k

.

The band gap selection can be used across the VDD

voltages while maximizing the VOUT voltage ranges.

For VDD voltages below the 2 × Gain × VBG voltage, the

output for the upper codes will be clipped to the VDD

voltage. Table 5-1 shows the maximum DAC register

code given device VDD and Gain bit setting.

Note 1: Any variation or noises on the reference

source can directly affect the DAC output.

The reference voltage needs to be as

clean as possible for accurate DAC

performance.

2: If the VREF pin is tied to the VDD voltage,

the VDD mode (VRnB:VRnA = 00) is

recommended.

Note 1: The Band Gap Voltage (VBG) is 1.22V

typical. The band gap output goes

through the buffer with a 2x gain to

create the VRL voltage. See Table 5-1

for additional information on the

band gap circuit.

VDD

VRL

Band Gap(1)

(1.227V typical)

VDD

VREF

PDnB:PDnA and

VRnB:VRnA

PDnB:PDnA and

VRnB:VRnA

PDnB:PDnA and

VRnB:VRnA

–

Note 1: The voltage source should have a low

output impedance. If the voltage source

has a high output impedance, then the

voltage on the VREF pin is lower than

expected. The resistor ladder has a

typical impedance of 140 k

 and a typical

capacitance of 29 pF.

2: If the VREF pin is tied to the VDD voltage,

the VDD mode (VRnB:VRnA = 00) is

recommended.

TABLE 5-1:

VOUT USING BAND GAP

Max DAC Code(1)

Comment

12-Bit 10-Bit 8-Bit

5.5

FFFh 3FFh FFh VOUT(max) = 2.44V(2)

FFFh 3FFh FFh VOUT(max) = 4.88V(2)

2.7

FFFh 3FFh FFh VOUT(max) = 2.44V(2)

8CDh 233h 8Ch ~ 0 to 56% range

Note 1:

Without the VOUT pin voltage being

clipped.

When VBG = 1.22V typical.

Band gap performance achieves full

performance starting from a VDD of 2.0V.

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