MCP48FVB28 datasheet(79/112 Pages) MICROCHIP

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DS20006362A-page 79

MCP48FXBX4/8

7.6

Error Condition

The Command Error (CMDERR) bit indicates if the five

Address bits received (AD4:AD0) and the two Com-

mand bits received (C1:C0) are a valid combination (see

Figures 7-1 and 7-2). The CMDERR bit is high if the

combination is valid and low if the combination is invalid.

The Command Error bit will also be low if a write to a

nonvolatile address has been specified and another

SPI command occurs before the CS pin is driven

inactive (VIH).

SPI commands that do not have a multiple of eight

clocks are ignored.

Once an error condition has occurred, any following

commands are ignored. All following SDO bits will be

low until the CMDERR condition is cleared by forcing

the CS pin to the Inactive state (VIH).

7.6.1

ABORTING A TRANSMISSION

All SPI transmissions must have the correct number of

SCK pulses to be executed. The command is not

executed until the complete number of clocks is

received. Some commands also require the CS pin to

be forced inactive (VIH). If the CS pin is forced to the

Inactive state (VIH), the serial interface is reset. Partial

commands are not executed.

SPI is more susceptible to noise than other bus

protocols. The most likely case is that noise corrupts

the value of the data being clocked into the

MCP48FXBX4/8 or the SCK pin is injected with extra

clock pulses. This may cause data to be corrupted in

the device, or a Command Error to occur, since the

address and command bits were not a valid combina-

tion. The extra SCK pulse will also cause the SPI data

(SDI) and clock (SCK) to be out of sync. Forcing the

CS pin to the Inactive state (VIH) resets the serial inter-

face. The SPI interface will ignore activity on the SDI

and SCK pins until the CS pin transition to the Active

state is detected (VIH to VIL or VIH to VIHH).

7.7

WRITE Command

(Normal and High Voltage)

WRITE commands are used to transfer data to the

desired memory location (from the host controller). The

WRITE command can be issued to both the volatile and

nonvolatile memory locations.

WRITE commands can be structured as either single or

continuous.

The format of the command is shown in Figure 7-3

(single) and Figure 7-6 (continuous).

A WRITE command to a volatile memory location

changes that location after a properly formatted WRITE

command has been received.

A WRITE command to a nonvolatile memory location

starts an EEPROM write cycle only after a properly for-

matted WRITE command has been received and the

CS pin transitions to the Inactive state (VIH).

7.7.1

SINGLE WRITE TO VOLATILE

MEMORY

The write operation requires that the CS pin be in the

Active state (VIL). Typically, the CS pin will be in the

Inactive state (VIH) and it is driven to the Active state

(VIL). The 24-bit WRITE command (command byte and

data bytes) is then clocked in on the SCK and SDI pins.

Once all 24 bits have been received, the specified

volatile address is updated. A write will not occur if the

WRITE command is not exactly 24 clock pulses. This

protects against system issues corrupting the

nonvolatile memory locations.

Figures 7-4 and 7-5 show the waveforms for a single

write (depending on the SPI mode).

Note 1: When the MCP48FXBX4/8 devices do not

receive data, it is recommended that the

CS pin be forced to the Inactive Level (VIL).

2: It is also recommended that long continu-

ous command strings be broken down

into single commands or shorter continu-

ous command strings. This reduces the

probability of noise on the SCK pin

corrupting the desired SPI commands.

Note 1: Writes to certain memory locations

depend on the state of the WiperLock™

technology status bits.

2: During device communication, if an

unimplemented address is specified, then

the MCP48FXBX4/8 will generate a

Command Error state. To reset the SPI

state machine, the CS pin must transition

to the Inactive state (VIH).

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