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MCP48FVB28 Arkusz danych(PDF) 87 Page - Microchip Technology

Numer części MCP48FVB28
Szczegółowy opis  8/10/12-Bit Quad/Octal Voltage Output, 6 LSb INL Digital-to-Analog Converters with SPI Interface
PDF  112 Pages
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Producent  MICROCHIP [Microchip Technology]
Strona internetowa  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP48FVB28 Arkusz danych(HTML) 87 Page - Microchip Technology

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 2020 Microchip Technology Inc.
DS20006362A-page 87
MCP48FXBX4/8
FIGURE 7-13:
8-Bit Enable Command (C1:C0 = 10) – SPI Waveforms (Mode 0,0).
7.10
Disable Configuration Bit
(High Voltage)
Figure 7-14 shows the formats for a single disable
Configuration bit command. The command will only
start an EEPROM Write Cycle (tWC) after a properly
formatted command has been received.
During an EEPROM write cycle, only serial commands
to volatile memory are accepted. All other serial
commands are ignored until the EEPROM Write Cycle
(tWC) completes. This allows the host controller to oper-
ate on the volatile DAC, the volatile VREF, Power-Down,
Gain and Status, and WiperLock Technology Status
registers. The EEWA bit in the Status register indicates
the status of an EEPROM write cycle.
FIGURE 7-14:
Disable Command Sequence.
AD2
AD1
AD4
AD3
C0
X
AD0
C1
07
06
03
01
02
00
05
CMDERR
CS
SDI
04
VIH
VIL
VIH
VIHH
SDO
SCK
HVC
Input
Sample
Note 1:
If an error condition occurs (CMDERR = 0), all the following SDO bits will be low until the CMDERR
condition is cleared (the CS pin is forced to the Inactive state).
2:
The CMDERR bit will be forced to ‘0’, regardless if this Address+Command combination is valid. This
command will not be completed and requires the CS pin to return to VIH to clear the CMDERR
condition.
AD
4
AD
3
AD
2
AD
1
AD
0
C
1
C
0
X
AD
4
AD
3
AD
2
AD
1
AD
0
C
1
C
0
X
AD
4
AD
3
AD
2
AD
1
AD
0
C
1
C
0
X
SDI *
**
**
0
1
**
**
**
0
1
**
**
**
0
1
*
SDO
XX
XX
XX
X
1
11
11
11
1
1
11
11
11
1
1 Valid(1)
XX
XX
XX
X
0
00
00
00
00
00
00
00
00 Invalid(2)



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