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AT25QL321

DS-25QL321–131C–5/2017

Figure 7-5. Read Status Register Instruction (QPI Mode)

7.6

Write Status Register (01h)

The Write Status Register instruction is to write only non-volatile Status Register-1 bits (SRP0) and Status Register-

2 bits (QE and SRP1). All other Status Register bit locations are read-only and will not be affected by the Write Status

A Write Enable instruction must previously have been issued prior to setting Write Status Register Instruction (Status

instruction code, and then writing the status register data byte as illustrated in Figure 7-6 and Figure 7-7.

The CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not done the Write

Status Register instruction will not be executed. If CS is driven high after the eighth clock, the CMP, QE and SRP1

(Status Register 2) bits will be cleared to 0. After CS is driven high, the self- timed Write Status Register cycle will

commence for a time duration of tw (See AC Characteristics).

While the Write Status Register cycle is in progress, the Read Status Register instruction may still be accessed to

check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a 0 when the

cycle is finished and ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable Latch

(WEL) bit in Status Register will be cleared to 0.

Figure 7-6. Write Status Register Instruction (SPI Mode)

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