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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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LT4295 Arkusz danych(PDF) 40 Page - Analog Devices |
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LT4295 Arkusz danych(HTML) 40 Page - Analog Devices |
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40 / 50 page  LTC9101-1/ LTC9102/LTC9103 40 Rev. 0 For more information www.analog.com APPLICATIONS INFORMATION If using the direct connection scheme, the 3.3V regu- lator that supplies the LTC9101-1 can also supply the LTC9102s/LTC9103s. This is the preferred option when the LTC9101-1 and LTC9102/LTC9103 are on the same side of the system isolation barrier. High-Speed Data Isolation The LTC9101-1/LTC9102/LTC9103 chipset can either pro- vide proprietary isolation or rely on existing system isola- tion. Significant BOM cost reductions can be achieved using the proprietary isolation scheme. In the proprietary isolation scheme, the LTC9101-1/ LTC9102/LTC9103 chipset uses transformers to isolate the LTC9101-1 from one to four LTC9102s/LTC9103s (see Figure 28). In this case, the SDAIN and SDAOUT pins can be shorted to each other and tied directly to the I2C/SMBus bus. The transformers should be 10BASE-T or 10/100BASE-T with a 1:1 turns ratio. Optimally, the selected transformers do not have common-mode chokes. These transformers typically provide 1500V of isolation between the LTC9101-1 and the LTC9102s/LTC9103s. For proper operation, strict layout guidelines must be met. 9101123 F26 C1 1µF 100V 1µF 100V 1µF 100V 1µF R1 10k 1/2W R3 10k 1/2W 1µF 47µF 100V R2 10k 1/2W R4 10k 1/2W + 1µF VEE VEE AGND CAP3 EXT3 LTC9102/LTC9103 VEE VEE VEE VEE VEE AGND CAP3 EXT3 CAP4 PWRIN LTC9102/LTC9103 C1 1µF 100V 1µF CAP4 PWRIN Figure 26. Power Supply Configuration with Internal 3.3V Supply 9101123 F27 1µF C1 1µF 100V C2 1µF 100V R1 10k 1/2W R2 10k 1/2W 1µF 1µF 100V 1µF 100V 1µF 47µF 100V + 1µF VEE VEE 3.3V VEE VEE AGND CAP3 EXT3 PWRIN CAP4 LTC9102/LTC9103 VEE 3.3V AGND CAP3 EXT3 PWRIN CAP4 LTC9102/LTC9103 3.3V REGULATOR Figure 27. Power Supply Configuration with External 3.3V Regulators In the direct connection scheme, the LTC9101-1/LTC9102/ LTC9103 chipset relies on pre-existing system isolation. In this scheme, the LTC9101-1 connects directly to one or more LTC9102s/LTC9103s using a proprietary com- munication protocol (see Figure 29). External MOSFET Careful selection of the power MOSFET is critical to sys- tem reliability. Choosing a MOSFET requires extensive analysis and testing of the MOSFET SOA curve against the various PSE current limit conditions. ADI recommends the PSMN075-100MSE for PSEs configured to deliver up to 51W maximum port power (single-signature) or 25.5W maximum pairset power (dual-signature). For PSEs configured to power up to 71.3W maximum port power (single-signature) or 35.6W maximum pairset power (dual-signature), ADI recommends the PSMN040- 100MSE. These MOSFETs are selected for their proven reliability in PoE applications. Contact ADI Applications before using a MOSFET other than one of these recom- mended parts. |
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